ADC11DS105

ADC11DS105 www.ti.com SNAS421C – FEBRUARY 2008 – REVISED APRIL 2013 ADC11DS105 Dual 11-Bit, 105 MSPS A/D Converter with Serial LVDS Outputs Check for Samples: ADC11DS105 FEATURES 1 2 Clock Duty Cycle Stabilizer Single +3.0 or +3.3V Supply Operation Serial LVDS Outputs Serial Control Interface Overrange Outputs 60-Pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch) APPLICATIONS High IF Sampling Receivers Wireless Base Station Receivers Test and Measurement Equipment Communications Instrumentation Portable Instrumentation KEY SPECIFICATIONS Resolution 11 Bits Conversion Rate 105 MSPS SNR (fIN = 240 MHz) 66 dBFS (typ) SFDR (fIN = 240 MHz) 82 dBFS (typ) Full Power Bandwidth 1 GHz (typ) Power Consumption 1 W (typ) DESCRIPTION The ADC11DS105is a high-performance CMOS analog-to-digital converters capable of converting two analog input signals into 11-bit digital words at rates up to 105 Mega Samples Per Second (MSPS). The digital outputs are serialized and provided on differential LVDS signal pairs. These converters use a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. The ADC11DS105 may be operated from a single +3.0 or +3.3V power supply. A powerdown feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential in...