Buffer Gate. SN74LVC125A Datasheet

SN74LVC125A Gate. Datasheet pdf. Equivalent


Part SN74LVC125A
Description Quadruple Bus Buffer Gate
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SN74LVC125A
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SN74LVC125A
SCAS290Q – JANUARY 1993 – REVISED JANUARY 2015
SN74LVC125A Quadruple Bus Buffer Gate With 3-State Outputs
1 Features
1 3-State Outputs
• Separate OE for all 4 buffers
• Operates From 1.65 V to 3.6 V
• Specified From –40°C to 85°C
and –40°C to 125°C
• Inputs Accept Voltages to 5.5 V
• Max tpd of 4.8 ns at 3.3 V
• Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
• Latch-Up Performance Exceeds 250 mA
Per JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 1000-V Charged-Device Model
2 Applications
• Cable Modem Termination Systems
• IP Phones: Wired and Wireless
• Optical Modules
• Optical Networking:
– EPON or Video Over Fiber
• Point-to-Point Microwave Backhaul
• Power: Telecom DC/DC Modules:
– Analog or Digital
• Private Branch Exchanges (PBX)
• TETRA Base Stations
• Telecom Base Band Units
• Telecom Shelters:
– Filter Unit s
– Power Distribution Units (PDU)
– Power Monitoring Units (PMU)
– Wireless Battery Monitoring
– Remote Electrical Tilt Units (RET)
– Remote Radio Units (RRU)
– Tower Mounted Amplifiers (TMA)
• Vector Signal Analyzers and Generators
• Video Conferencing: IP-Based HD
• WiMAX and Wireless Infrastructure Equipment
• Wireless Communications Testers
• xDSL Modems and DSLAM
3 Description
This quadruple bus buffer gate is designed for 1.65-V
to 3.6-V VCC operation.
The SN74LVC125A device features independent line
drivers with 3-state outputs. Each output is disabled
when the associated output-enable (OE) input is high.
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
Inputs can be driven from either 3.3-V or 5-V devices.
This feature allows the use of this device as a
translator in a mixed 3.3-V/5-V system environment.
PART NUMBER
SN74LVC125A
Device Information(1)
PACKAGE (PIN)
BODY SIZE
SOIC (14)
8.65 mm × 3.91 mm
SSOP (14)
6.20 mm × 5.30 mm
SOP (14)
10.30 mm × 5.30 mm
TSSOP (14)
5.00 mm × 4.40 mm
VQFN (14)
3.50 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
1OE
3OE
1A
1Y
3A
3Y
2OE
4OE
2A
2Y
4A
4Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



SN74LVC125A
SN74LVC125A
SCAS290Q – JANUARY 1993 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Simplified Schematic............................................. 1
5 Revision History..................................................... 2
6 Pin Configuration and Functions ......................... 3
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ..................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions ...................... 5
7.4 Thermal Information .................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Switching Characteristics .......................................... 6
7.7 Operating Characteristics.......................................... 6
7.8 Typical Characteristics .............................................. 7
8 Parameter Measurement Information .................. 8
9 Detailed Description .............................................. 9
9.1 Overview ................................................................... 9
9.2 Functional Block Diagram ......................................... 9
9.3 Feature Description................................................... 9
9.4 Device Functional Modes.......................................... 9
10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
10.2 Typical Application ............................................... 10
11 Power Supply Recommendations ..................... 11
12 Layout................................................................... 11
12.1 Layout Guidelines ................................................. 11
12.2 Layout Example .................................................... 12
13 Device and Documentation Support ................. 13
13.1 Trademarks ........................................................... 13
13.2 Electrostatic Discharge Caution ............................ 13
13.3 Glossary ................................................................ 13
14 Mechanical, Packaging, and Orderable
Information ........................................................... 13
5 Revision History
Changes from Revision P (October 2010) to Revision Q
Page
• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
• Deleted Ordering Information table. ....................................................................................................................................... 1
2
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