Buffer Gate. SN74LVC125A-EP Datasheet

SN74LVC125A-EP Gate. Datasheet pdf. Equivalent


Part SN74LVC125A-EP
Description Quadruple Bus Buffer Gate
Feature www.ti.com FEATURES • Controlled Baseline – One Assembly/Test Site, One Fabrication Site • Enhanced .
Manufacture etcTI
Datasheet
Download SN74LVC125A-EP Datasheet


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SN74LVC125A-EP
www.ti.com
FEATURES
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.8 ns at 3.3 V
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
SN74LVC125A-EP
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCAS739C – DECEMBER 2003 – REVISED DECEMBER 2006
Typical VOHV (Output VOH Undershoot) >2 V at
VCC = 3.3 V, TA = 25°C
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
PW PACKAGE
(TOP VIEW)
1OE 1
1A 2
1Y 3
2OE 4
2A 5
2Y 6
GND 7
14 VCC
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8 3Y
DESCRIPTION/ORDERING INFORMATION
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC125A features independent line drivers with 3-state outputs. Each output is disabled when the
associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
TA
–40°C to 85°C
–55°C to 125°C
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER
TSSOP – PW
TSSOP – PW
Reel of 2000
Reel of 2000
SN74LVC125AIPWREP
SN74LVC125AMPWREP (2)
SOIC – D
Reel of 2500
SN74LVC125AMDREP
TOP-SIDE MARKING
C125AEP
125AMEP
125AMEP
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) Product Preview
FUNCTION TABLE
(EACH BUFFER)
INPUTS
OE
A
L
H
L
L
H
X
OUTPUT
Y
H
L
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2006, Texas Instruments Incorporated



SN74LVC125A-EP
SN74LVC125A-EP
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCAS739C – DECEMBER 2003 – REVISED DECEMBER 2006
LOGIC DIAGRAM (POSITIVE LOGIC)
1OE 1
3OE 10
2
1A
3
1Y
9
3A
2OE 4
5
2A
6
2Y
4OE 13
12
4A
www.ti.com
8
3Y
11
4Y
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
VI
Input voltage range(2)
VO
Output voltage range(2)(3)
IIK
Input clamp current
IOK
Output clamp current
IO
Continuous output current
Continuous current through VCC or GND
θJA
Package thermal impedance(4)
Tstg
Storage temperature range
VI < 0
VO < 0
MIN
MAX UNIT
–0.5
6.5 V
–0.5
6.5 V
–0.5 VCC + 0.5
V
–50 mA
–50 mA
±50 mA
±100 mA
113 °C/W
–65
150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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