POSITIVE-NAND GATE. SN74LVC10A Datasheet

SN74LVC10A GATE. Datasheet pdf. Equivalent


Part SN74LVC10A
Description TRIPLE 3-INPUT POSITIVE-NAND GATE
Feature www.ti.com FEATURES • Operates From 1.65 V to 3.6 V • Specified From –40°C to 85°C and – 40°C to 125.
Manufacture etcTI
Datasheet
Download SN74LVC10A Datasheet


www.ti.com FEATURES • Operates From 1.65 V to 3.6 V • Specif SN74LVC10A Datasheet
Recommendation Recommendation Datasheet SN74LVC10A Datasheet




SN74LVC10A
www.ti.com
FEATURES
Operates From 1.65 V to 3.6 V
Specified From –40°C to 85°C and
– 40°C to 125°C
Inputs Accept Voltages to 5.5 V
Max tpd of 4.9 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
SN74LVC10A
TRIPLE 3-INPUT POSITIVE-NAND GATE
SCAS284O – JANUARY 1993 – REVISED JULY 2005
D, DB, NS, OR PW PACKAGE
(TOP VIEW)
1A 1
1B 2
2A 3
2B 4
2C 5
2Y 6
GND 7
14 VCC
13 1C
12 1Y
11 3C
10 3B
9 3A
8 3Y
RGY PACKAGE
(TOP VIEW)
1
1B 2
2A 3
2B 4
2C 5
2Y 6
7
14
13 1C
12 1Y
11 3C
10 3B
9 3A
8
DESCRIPTION/ORDERING INFORMATION
This triple 3-input positive-NAND gate is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC10A performs the Boolean function Y = A B C or Y = A + B + C in positive logic.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
TA
–40°C to 85°C
–40°C to 125°C
QFN – RGY
SOIC – D
SOP – NS
SSOP – DB
TSSOP – PW
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER
Reel of 1000
SN74LVC10ARGYR
Tube of 50
SN74LVC10AD
Reel of 2500
SN74LVC10ADR
Reel of 250
SN74LVC10ADT
Reel of 2000
SN74LVC10ANSR
Reel of 2000
SN74LVC10ADBR
Tube of 90
SN74LVC10APW
Reel of 2000
SN74LVC10APWR
Reel of 250
SN74LVC10APWT
TOP-SIDE MARKING
LC10A
LVC10A
LVC10A
LC10A
LC10A
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1993–2005, Texas Instruments Incorporated



SN74LVC10A
SN74LVC10A
TRIPLE 3-INPUT POSITIVE-NAND GATE
SCAS284O – JANUARY 1993 – REVISED JULY 2005
FUNCTION TABLE
(EACH GATE)
INPUTS
A
B
C
H
H
H
L
X
X
X
L
X
X
X
L
OUTPUT
Y
L
H
H
H
LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)
A
B
Y
C
www.ti.com
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
VI
Input voltage range(2)
VO
Output voltage range(2)(3)
IIK
Input clamp current
IOK
Output clamp current
IO
Continuous output current
Continuous current through VCC or GND
θJA
Package thermal impedance
Tstg
Storage temperature range
Ptot
Power dissipation
VI < 0
VO < 0
D package (4)
DB package(4)
NS package(4)
PW package(4)
RGY package(5)
TA = –40°C to 125°C(6)(7)
MIN
MAX
–0.5
6.5
–0.5
6.5
–0.5 VCC + 0.5
–50
–50
±50
±100
86
96
76
113
47
–65
150
500
UNIT
V
V
V
mA
mA
mA
mA
°C/W
°C
mW
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.
(6) For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K.
(7) For the DB, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K.
2







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