SN74F1056

D Designed to Reduce Reflection Noise D Repetitive Peak Forward Current 300 mA D 8-Bit Array Structure Suited for Bus-Oriented Systems description This Schottky barrier diode bus-termination array is designed to reduce reflection noise on memory bus lines. This device consists of an 8-bit high-speed Schottky diode array suitable for a clamp to GND. The SN74F1056 is characterized for operation from 0°C to 70°C. schematic diagrams 1 D01 SC Package 2 D02 3 D03 4 D04 7 D05 8 D06 9 D07 10 D08 6 GND 5 GND SN74F1056 8-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDFS085A – AUGUST 1992 – REVISED JULY 1997 SC PACKAGE (TOP VIEW) D01 1 D02 2 D03 3 D04 4 GND 5 GND 6 D05 7 D06 8 D07 9 D08 10 D PACKAGE (TOP VIEW) D01 1 D02 2 D03 3 D04 4 D05 5 D06 6 D07 7 D08 8 16 NC 15 GND 14 GND 13 GND 12 GND 11 GND 10 GND 9 NC 1 D01 2 D02 3 D03 4 D04 5 D05 6 D06 7 D07 8 D08 D Package 15 GND 14 GND 13 GND 12 GND 11 GND 10 GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright © 1997, Texas Instruments Incorporated 1 SN74F1056 8-BIT...