BUFFER GATE. SN74F126 Datasheet

SN74F126 GATE. Datasheet pdf. Equivalent


Part SN74F126
Description QUADRUPLE BUS BUFFER GATE
Feature SN74F126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SDFS017B – JANUARY 1989 – REVISED NOVEMBER 2.
Manufacture etcTI
Datasheet
Download SN74F126 Datasheet


SN74F126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SDFS SN74F126 Datasheet
Recommendation Recommendation Datasheet SN74F126 Datasheet




SN74F126
SN74F126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SDFS017B – JANUARY 1989 – REVISED NOVEMBER 2002
D 4.5-V to 5.5-V VCC Operation
D Max tpd of 6.5 ns at 5 V
D 3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
description/ordering information
The SN74F126 bus buffer features independent
line drivers with 3-state outputs. Each output is
disabled when the associated output-enable (OE)
input is low.
D, N, OR NS PACKAGE
(TOP VIEW)
1OE 1
1A 2
1Y 3
2OE 4
2A 5
2Y 6
GND 7
14 VCC
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8 3Y
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube
SN74F126N
SN74F126N
0°C to 70°C SOIC – D
Tube
Tape and reel
SN74F126D
SN74F126DR
F126
SOP – NS
Tape and reel
SN74F126NSR
74F126
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each buffer)
INPUTS
OE
A
OUTPUT
Y
H
H
H
H
L
L
L
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2002, Texas Instruments Incorporated
1



SN74F126
SN74F126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SDFS017B JANUARY 1989 REVISED NOVEMBER 2002
logic diagram (positive logic)
1
1OE
2
1A
4
2OE
5
2A
10
3OE
9
3A
13
4OE
12
4A
3
1Y
6
2Y
8
3Y
11
4Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 V to 7 V
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA to 5 mA
Voltage range applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input voltage ratings may be exceeded provided the input current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN NOM MAX UNIT
VCC Supply voltage
4.5
5 5.5 V
VIH High-level input voltage
2
V
VIL
Low-level input voltage
0.8 V
IIK
Input clamp current
18 mA
IOH High-level output current
15 mA
IOL
Low-level output current
64 mA
TA
Operating free-air temperature
0
70 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265







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