Document
STB12NM50ND STD12NM50ND, STF12NM50ND
N-channel 500 V, 0.29 Ω, 11 A, FDmesh™ II Power MOSFET (with fast diode) in D2PAK, DPAK, TO-220FP
Features
Type
VDSS (@Tjmax) RDS(on) max ID
STB12NM50ND
550 V
0.38 Ω 11 A
STD12NM50ND 550 V
0.38 Ω 11 A
STF12NM50ND
550 V
0.38 Ω 11 A
■ 100% avalanche tested ■ Low input capacitance and gate charge ■ Low gate input resistance
Application
■ Switching applications
Description
FDmesh™ technology combines the MDmesh™ features with an intrinsic fast-recovery body diode. The resulting product has reduced onresistance and fast switching commutations, making it especially suitable for bridge topologies where low trr is required.
3 1
D2PAK
3 1
DPAK
3 2 1
TO-220FP
Figure 1. Internal schematic diagram
$ '
Table 1. Device summary Order codes
Marking
STB12NM50ND STD12NM50ND STF12NM50ND
12NM50ND 12NM50ND 12NM50ND
3
!-V
Package D2PAK DPAK
TO-220FP
Packaging Tape and reel Tape and reel
Tube
June 2009
Doc ID 14936 Rev 2
1/16
www.st.com
16
Contents
Contents
STB12NM50ND, STD12NM50ND, STF12NM50ND
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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Doc ID 14936 Rev 2
STB12NM50ND, STD12NM50ND, STF12NM50ND
1
Electrical ratings
Electrical ratings
Table 2. Absolute maximum ratings
Symbol
Parameter
VDS Drain-source voltage (VGS=0)
VGS Gate-source voltage
ID Drain current (continuous) at TC = 25 °C
ID Drain current (continuous) at TC = 100 °C IDM (2) Drain current (pulsed)
PTOT Total dissipation at TC = 25 °C
VISO dv/dt (3)
Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1 s;TC=25 °C)
Peak diode recovery voltage slope
Tstg Storage temperature Tj Operating junction temperature
1. Limited only by maximum temperature allowed 2. Pulse width limited by safe operating area 3. ISD ≤ 11 A, di/dt ≤ 600 A/µs, VDD = 80% V(BR)DSS
Value
D²PAK
DPAK
500 ± 25 11 6.9 44 100
TO-220FP
11 (1) 6.9 (1) 44 (1)
25
2500
40 -55 to 150
150
Unit
V V A A A W
V
V/ns °C °C
Table 3. Thermal data
Symbol
Parameter
Rthj-case Thermal resistance junction-case max
Rthj-pcb Thermal resistance junction-pcb max
Rthj-amb Thermal resistance junction-amb max
Tl
Maximum lead temperature for soldering purposes
Value
D²PAK
DPAK
1.25
30
50
Unit TO-220FP
5
°C/W
°C/W
62.5
°C/W
300
°C
Table 4. Symbol
Avalanche characteristics Parameter
IAS
Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max)
Single pulse avalanche energy EAS (starting Tj = 25 °C, ID = IAS, VDD = 50 V)
Max value
Unit
5
A
350
mJ
Doc ID 14936 Rev 2
3/16
Electrical characteristics
STB12NM50ND, STD12NM50ND, STF12NM50ND
2
Electrical characteristics
(TCASE = 25 °C unless otherwise specified)
Table 5. Symbol
On/off states Parameter
Test conditions
Min. Typ. Max. Unit
V(BR)DSS
Drain-source breakdown voltage
ID = 1 mA, VGS= 0
500
dv/dt(1) Drain-source voltage slope VDD = 400 V,ID = 11 A, VGS = 10 V
IDSS
Zero gate voltage drain current (VGS = 0)
VDS = Max rating, VDS = Max rating,@125 °C
IGSS
Gate body leakage current
(VDS = 0)
VGS = ±20 V
VGS(th) Gate threshold voltage
VDS= VGS, ID = 250 µA
3
RDS(on)
Static drain-source on resistance
VGS= 10 V, ID= 5.5 A
1. Value measured at turn off under inductive load
44
4 0.29
1 100 100
5 0.38
V
V/ns µA µA nA V Ω
Table 6. Dynamic
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
gfs(1)
Ciss Coss Crss
Forward transconductance
Input capacitance Output capacitance Reverse transfer capacitance
VDS =15 V, ID= 5.5 A
VDS = 50 V, f =1 MHz, VGS = 0
-
8
-
S
850
pF
-
48
-
pF
5
pF
Coss
(2) eq.
Equivalent output capacitance
VGS = 0, VDS = 0 to 400 V
- 100
-
pF
Rg Gate input resistance
f=1 MHz Gate DC Bias=0
Test signal level=20 mV
-
4.5
-
Ω
open drain
Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge
VDD = 400 V, ID = 11 A VGS = 10 V Figure 19
30
nC
-
6
-
nC
17
nC
1. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS
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Doc ID 14936 Rev 2
STB12NM50ND, STD12NM50ND, STF12NM50ND
Electrical characteristics
Table 7. Symbol
Switching times Par.