IDT74ALVCH16721

IDT74ALVCH16721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD INDUSTRIAL TEMPERATURE RANGE IDT74ALVCH16721 FEATURES: 0.5 MICRON CMOS Technology Typical tSK(o) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) VCC = 3.3V ± 0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range VCC = 2.5V ± 0.2V CMOS power levels (0.4μ W typ. static) Rail-to-Rail output swing for increased noise margin Available in TSSOP package DRIVE FEATURES: High Output Drivers: ±24mA Low switching noise APPLICATIONS: 3.3V high speed systems 3.3V and lower voltage computing systems DESCRIPTION: This 20-bit flip-flop is built using advanced dual metal CMOS technology. The 20 flip-flops of the ALVCH16721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN) input is low. If CLKEN is high, no data is stored. A buffered output-enable (OE) input places the 20 outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The highimpedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old d...