SN54AS10

SN54ALS10A, SN54AS10, SN74ALS10A, SN74AS10 TRIPLE 3ĆINPUT POSITIVEĆNAND GATES Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs description These devices contain three independent 3-input positive-NAND gates. They perform the Boolean functions Y = A B C or Y = A + B + C in positive logic. The SN54ALS10A and SN54AS10 are characterized for operation over the full military temperature range of − 55°C to 125°C. The SN74ALS10A and SN74AS10 are characterized for operation from 0°C to 70°C. FUNCTION TABLE (each gate) INPUTS A B C OUTPUT Y H H H L L X X H X L X H X X L H logic symbol† 1 1A & 2 1B 13 1C 3 2A 4 2B 5 2C 9 3A 10 3B 11 3C 12 1Y 6 2Y 8 3Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. SDAS002B − MARCH 1984 − REVISED DECEMBER 1994 SN54ALS10A, SN54AS10 . . . J PACKAGE SN74ALS10A, SN74AS10 . . . D OR N PACKAGE (TOP VIEW) 1A 1 1B 2 2A 3 2B 4 2C 5 2Y 6 GND 7 14 VCC 13 1C 12 1Y 11 3C 10 3B 9 3A 8 3Y SN54ALS10A, SN54AS10 . . . FK PACKAGE (TOP VIEW) 1C VCC NC 1A 1B 3 2 1 20 19 2A 4 18 1Y NC 5 17 NC 2B 6 16 3C NC 7 15 NC 2C 8 14 3B 9 10 11 12 13 3A 3Y NC GND 2Y NC − No internal connection logic diagram (positive logic) 1 1A 2 1B 1C 13 2A 3 2B 4 2C 5 3A 9 3B 10 11 3C 12 1Y 6 2Y 8 3Y PRODUCTION DATA information is current as of pu...