SN54ALS138A, SN54AS138, SN74ALS138A, SN74AS138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SDAS055E – APRIL 1982 – REVISED...
SN54ALS138A, SN54AS138, SN74ALS138A, SN74AS138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SDAS055E – APRIL 1982 – REVISED JULY 1996
D Designed Specifically for High-Speed
Memory Decoders and Data Transmission Systems
D Incorporate Three Enable Inputs to Simplify
Cascading and /or Data Reception
D Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
description
The ′ALS138A and ′AS138 are 3-line to 8-line decoders/demultiplexers designed for highperformance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance systems, these devices can be used to minimize the effects of system decoding. When employed with high-speed memories with a fast enable circuit, the delay times of the decoder and the enable time of the memory are usually less than the typical access time of the memory. The effective system delay introduced by the
Schottky-clamped system decoder is negligible.
SN54ALS138A, SN54AS138 . . . J PACKAGE SN74ALS138A, SN74AS138 . . . D OR N PACKAGE
(TOP VIEW)
A1 B2 C3 G2A 4 G2B 5 G1 6 Y7 7 GND 8
16 VCC 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6
SN54ALS138A, SN54AS138 . . . FK PACKAGE (TOP VIEW)
Y0
VCC
NC
A
B
C G2A
NC G2B
G1
3 2 1 20 19
4
18 Y1
5
17 Y2
6
16 NC
7
15 Y3
8
14 Y4
9 10 11 12 13
Y5
Y6
NC
GND
Y7
The conditions at the binary-select (A, B, and C)
inputs and the three enable (G1, G2A, and G2B)
inputs...
