SN54AS286

Generate Either Odd or Even Parity for Nine Data Lines Cascadable for n-Bit Parity Direct Bus Connection for Parity Generation or Checking by Using the Parity I/O Port Glitch-Free Bus During Power Up/Down Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs description SN54AS286, SN74AS286 9ĆBIT PARITY GENERATORS/CHECKERS WITH BUSĆDRIVER PARITY I/O PORT SDAS050B − DECEMBER 1983 − REVISED DECEMBER 1994 SN54AS286 . . . J PACKAGE SN74AS286 . . . D OR N PACKAGE (TOP VIEW) G1 H2 XMIT 3 I4 PARITY ERROR 5 PARITY I/O 6 GND 7 14 VCC 13 F 12 E 11 D 10 C 9B 8A SN54AS286 . . . FK PACKAGE (TOP VIEW) The SN54AS286 and SN74AS286 universal 9-bit parity generators/checkers feature a local output for parity checking and a 48-mA bus-driving parity input/output (I/O) port for parity generation/checking. The word-length capability is easily expanded by cascading. The transmit (XMIT) control input is implemented specifically to accommodate cascading. When XMIT is low, the parity tree is disabled and PARITY ERROR remains at a high logic level regardless of the input levels. When XMIT is high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs ( A−I ) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level. H XMIT NC I NC PARITY ERROR 3 2 1 20 19 4 18 E ...