9DB833

DATASHEET EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3 9DB833 Description The 9DB833 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB833 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. Typical Applications 8 output PCIe Gen1–3 zero delay/fanout buffer Output Features 8 0.7V current-mode differential HCSL output pairs Supports zero delay buffer mode and fanout mode Selectable bandwidth 50–110MHz operation in PLL mode 5–166MHz operation in Bypass mode Features 3 selectable SMBus addresses; multiple devices can share the same SMBus segment OE# pins; suitable for Express Card applications PLL or bypass mode; PLL can dejitter incoming clock Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs Spread spectrum compatible; tracks spreading input clock for low EMI SMBus interface; unused outputs can be disabled Supports undriven differential outputs in Power Down mode for power management Key Specifications Outputs cycle-cycle jitter <50ps Output to output skew <50ps Phase jitter: PCIe Gen3 <1.0ps rms Block Diagram 8 OE(7:0)# SRC_IN SRC_IN# SPREAD COMPATIBLE PLL M U X STOP 8 LOGIC DIF(7:0)) PD# BYP#_LOBW_HIBW SMBDAT SMBCLK CONTROL LOGIC IREF LOCK IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3 1 9DB833 MAY 25, 2018 9DB833 EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3 Pin Config...