Document
D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
D Support Mixed-Mode Voltage Operation on
All Ports
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS
WITH 3ĆSTATE OUTPUTS
SCLS398G − APRIL 1998 − REVISED APRIL 2005
SN54LV367A . . . J OR W PACKAGE SN74LV367A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
1OE 1 1A1 2 1Y1 3 1A2 4 1Y2 5 1A3 6 1Y3 7 GND 8
16 VCC 15 2OE 14 2A2 13 2Y2 12 2A1 11 2Y1 10 1A4 9 1Y4
SN54LV367A . . . FK PACKAGE (TOP VIEW)
1A1 1OE NC VCC 2OE
description/ordering information
The ’LV367A devices are hex buffers and line drivers designed for 2-V to 5.5-V VCC operation. These devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
1Y1
3 2 1 20 19
4
18
2A2
1A2 5
17 2Y2
NC 6
16 NC
1Y2 7
15 2A1
1A3 8
14 2Y1
9 10 11 12 13
1Y3 GND
NC 1Y4 1A4
The ’LV367A devices are organized as dual 4-line and 2-line buffers/drivers with active-low output-enable (1OE and 2OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.
NC − No internal connection
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE PART NUMBER
TOP-SIDE MARKING
SOIC − D
Tube of 40 Reel of 2500
SN74LV367AD SN74LV367ADR
LV367A
SOP − NS
Reel of 2000 SN74LV367ANSR 74LV367A
−40°C to 85°C
SSOP − DB TSSOP − PW
Reel of 2000 Reel of 2000 Reel of 250
SN74LV367ADBR SN74LV367APWR SN74LV367APWT
LV36A LV367A
TVSOP − DGV Reel of 2000 SN74LV367ADGVR LV367A
CDIP − J
Tube of 25
SNJ54LV367AJ
SNJ54LV367AJ
−55°C to 125°C CFP − W
Tube of 150
SNJ54LV367AW
SNJ54LV367AW
LCCC − FK
Tube of 55
SNJ54LV367AFK
SNJ54LV367AFK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2005, Texas Instruments Incorporated 1
SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS WITH 3ĆSTATE OUTPUTS
SCLS398G − APRIL 1998 − REVISED APRIL 2005
FUNCTION TABLE (each buffer/driver)
INPUTS
OE
A
OUTPUT Y
L
H
H
L
L
L
H
X
Z
logic diagram (positive logic)
1OE 1
2OE 15
2 1A1
3 1Y1
12 2A1
11 2Y1
To Three Other Channels Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
To One Other Channel
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high-impedance or
power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range applied in the high or low state, VO (see Notes 1 and 2) . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DB package . .