SN74LV74A-Q1

SN74LV74A-Q1 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP D Qualified for Automotive Applications D 2-V to 5.5-V VCC Operation D Max tpd of 13 ns at 5 V D Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C D Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C D Support Mixed-Mode Voltage Operation on All Ports D Ioff Supports Partial-Power-Down Mode Operation D Latch-Up Performance Exceeds 250 mA Per JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) SCLS556B − DECEMBER 2003 − REVISED APRIL 2008 D OR PW PACKAGE (TOP VIEW) 1CLR 1 1D 2 1CLK 3 1PRE 4 1Q 5 1Q 6 GND 7 14 VCC 13 2CLR 12 2D 11 2CLK 10 2PRE 9 2Q 8 2Q description/ordering informationS This dual positive-edge-triggered D-type flip-flop is designed for 2-V to 5.5-V VCC operation. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioff ci...