SN74AHC373N

D Operating Range 2-V to 5.5-V VCC D Latch-Up Performance Exceeds 250 mA Per JESD 17 SN54AHC373 . . . J OR W PACKAGE SN74AHC373 . . . DB, DGV, DW, N, NS, OR PW PACKAGE (TOP VIEW) SN54AHC373, SN74AHC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS235I – OCTOBER 1995 – REVISED JULY 2003 D ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) SN54AHC373 . . . FK PACKAGE (TOP VIEW) 8Q VCC OE 1Q 1D OE 1 1Q 2 1D 3 2D 4 2Q 5 3Q 6 3D 7 4D 8 4Q 9 GND 10 20 VCC 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 LE 4Q GND LE 2D 3 2 1 20 19 4 18 8D 2Q 5 17 7D 3Q 6 16 7Q 3D 7 15 6Q 4D 8 14 6D 9 10 11 12 13 5Q 5D description/ordering information The ’AHC373 devices are octal transparent D-type latches designed for 2-V to 5.5-V VCC operation. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – N Tube SN74AHC373N S...