Document
SN54AHC74, SN74AHC74
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SCLS255K – DECEMBER 1995 – REVISED DECEMBER 2013
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
Check for Samples: SN54AHC74, SN74AHC74
FEATURES
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• Operating Range 2-V to 5.5-V VCC • Latch-Up Performance Exceeds 250 mA Per
JESD 17 • ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)
DESCRIPTION
The ’AHC74 dual positive-edge-triggered devices are D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1995–2013, Texas Instruments Incorporated
SN54AHC74, SN74AHC74
SCLS255K – DECEMBER 1995 – REVISED DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. Function Table (Each Flip-Flop)
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H (1)
H (1)
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
(1) This configuration is unstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.
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SN54AHC74, SN74AHC74
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SCLS255K – DECEMBER 1995 – REVISED DECEMBER 2013
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Supply voltage range, VCC Input voltage range, VI ((2)) Output voltage range, VO ((2)) Input clamp current, IIK (VI < 0) Output clamp current, IOK (VO < 0 or VO > VCC) Continuous output current, IO (VO = 0 to VCC) Continuous current through VCC or GND
Package thermal impedance, ΘJA
Storage temperature range, Tstg
D package DB package(3) DGV package(3) N package(3) NS package(3) PW package(3) RGY package(4)
UNIT –0.5 V to 7 V –0.5 V to 7 V –0.5 V to VCC + 0.5 V
–20 mA ±20 mA ±25 mA ±50 mA 86°C/W 96°C/W 127°C/W 80°C/W 76°C/W 113°C/W 47°C/W –65°C to 150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) The package thermal impedance is calculated in accordance with JESD 51-7. (4) The package thermal impedance is calculated in accordance with JESD 51-5.
Recommended Operating Conditions(1)
VCC VIH
VIL VI VO IOH
IOL Δt/Δv
TA
Supply voltage
High-level input voltage
Low-level input voltage Input voltage
VCC = 2 V VCC = 3V VCC = 5.5 V VCC = 2 V VCC = 3 V VCC = 5.5 V
Output voltage
VCC = 2 V
High-level output current
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
VCC = 2 V
Low-level output current
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
Input transition rise or fall rate VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V
Operating free-air temperature
SN54AHC74 MIN 2 1.5 2.1 3.85
0 0
–55
MAX 5.5
0.5 0.9 1.65 5.5 VCC –50 –4 –8 50
4 8 100 20 125
SN74AHC74 MIN 2 1.5 2.1 3.85
0 0
–40
MAX 5.5
0.5 0.9 1.65 5.5 VCC –50 –4 –8 50
4 8 100 20 125
UNIT V
V
V
V V µA mA µA mA
ns/V °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 1995–2013, Texas Instruments Incorporated
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Product Folder Links: SN54AHC74 SN74AHC74
SN54AHC74, SN74AHC74
SCLS255K – DECEMBER 1995 – REVISED DECEMBER 2013
www.ti.com
Electrical Characteristics
over recommended operating free-air te.