Data sheet acquired from Harris Semiconductor SCHS149F
September 1997 - Revised November 2003
CD54HC147, CD74HC147, CD7...
Data sheet acquired from Harris Semiconductor SCHS149F
September 1997 - Revised November 2003
CD54HC147, CD74HC147, CD74HCT147
High-Speed CMOS Logic 10- to 4-Line Priority Encoder
[ /Title (CD74 HC147 , CD74 HCT14 7) /Subject (High Speed CMOS Logic 10-to-4 Line Priority Encode r) /Autho r () /Keywords (High Speed CMOS Logic 10-to-4 Line Priority Encode r, High Speed CMOS Logic 10-to-4 Line Priority
Features
Buffered Inputs and Outputs
Typical Propagation Delay: CL = 15pF, TA = 25oC
13ns
at
VCC
=
5V,
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55oC to 125oC
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Description
The ’HC147 and CD74HCT147 are high speed silicon-gate CMOS devices and are pin-compatible with low power
Schottky TTL (LSTTL).
The ’HC147 and CD74HCT147 9-input priority encoders accept data from nine active LOW inputs (l1 to l9) and
provide binary representation on the four active LOW inputs (Y0 to Y3). A priority is assigned to each input so that when two or more inputs are si...