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74AHC573PW Dataheets PDF



Part Number 74AHC573PW
Manufacturers nexperia
Logo nexperia
Description Octal D-type transparant latch
Datasheet 74AHC573PW Datasheet74AHC573PW Datasheet (PDF)

74AHC573; 74AHCT573 Octal D-type transparent latch; 3-state Rev. 8 — 13 July 2020 Product data sheet 1. General description The 74AHC573; 74AHCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the informatio.

  74AHC573PW   74AHC573PW


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74AHC573; 74AHCT573 Octal D-type transparent latch; 3-state Rev. 8 — 13 July 2020 Product data sheet 1. General description The 74AHC573; 74AHCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. 2. Features and benefits • Wide supply voltage range from 2.0 V to 5.5 V • Balanced propagation delays • All inputs have Schmitt-trigger action • Overvoltage tolerant inputs to 5.5 V • High noise immunity • CMOS low power dissipation • Common 3-state output enable input • Functionally identical to the 74AHC373; 74AHCT373 • Input levels: • For 74AHC573: CMOS input level • For 74AHCT573: TTL input level • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22-C101E exceeds 1000 V • Latch-up performance exceeds 100 mA per JESD 78 Class II Level A • Multiple package options • Specified from -40 °C to +85 °C and from -40 °C to +125 °C Nexperia 74AHC573; 74AHCT573 Octal D-type transparent latch; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description 74AHC573D 74AHCT573D -40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm 74AHC573PW 74AHCT573PW -40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm 74AHC573BQ 74AHCT573BQ -40 °C to +125 °C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm Version SOT163-1 SOT360-1 SOT764-1 4. Functional diagram Fig. 1. Functional diagram 2 D0 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 11 LE 1 OE 1 2 OE D0 Q0 19 3 D1 Q1 18 4 D2 Q2 17 5 D3 Q3 16 6 D4 Q4 15 7 D5 Q5 14 8 D6 Q6 13 9 D7 Q7 12 LE 11 mna807 Fig. 2. Logic symbol LATCH 1 to 8 3-STATE OUTPUTS Q0 19 Q1 18 Q2 17 Q3 16 Q4 15 Q5 14 Q6 13 Q7 12 mna809 11 C1 1 EN1 2 1D 3 4 5 6 7 8 9 Fig. 3. IEC logic symbol 19 18 17 16 15 14 13 12 mna808 74AHC_AHCT573 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 13 July 2020 © Nexperia B.V. 2020. All rights reserved 2 / 16 Nexperia 74AHC573; 74AHCT573 Octal D-type transparent latch; 3-state D0 D1 D2 D3 D4 D5 D6 D7 DQ LATCH 1 LE LE DQ LATCH 2 LE LE DQ LATCH 3 LE LE DQ LATCH 4 LE LE DQ LATCH 5 LE LE DQ LATCH 6 LE LE DQ LATCH 7 LE LE DQ LATCH 8 LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna810 Fig. 4. Logic diagram 5. Pinning information 5.1. Pinning 74AHC573 74AHCT573 OE 1 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 GND 10 20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 LE 001aad099 Fig. 5. Pin configuration SOT163-1 (SO20) and SOT360-1 (TSSOP20) terminal 1 index area 74AHC573 74AHCT573 1 OE 20 VCC D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 GND(1) 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 GND 10 LE 11 001aal532 Fig. 6. Transparent top view (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. Pin configuration SOT764-1 (DHVQFN20) 74AHC_AHCT573 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 13 July 2020 © Nexperia B.V. 2020. All rights reserved 3 / 16 Nexperia 74AHC573; 74AHCT573 Octal D-type transparent latch; 3-state 5.2. Pin description Table 2. Pin description Symbol OE D0 to D7 GND LE Q0 to Q7 VCC Pin 1 2, 3, 4, 5, 6, 7, 8, 9 10 11 19, 18, 17, 16, 15, 14, 13, 12 20 Description output enable input (active LOW) data input ground (0 V) latch enable (active HIGH) data output supply voltage 6. Functional description Table 3. Function table H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state. Operating mode Input Internal latch OE LE Dn Enable and read register (transparent mode) L H L L H H Latch and read register L L l L h H Latch register and disable outputs H L l L h H Output Qn L H L H Z Z 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134)..


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