74HC10D

74HC10; 74HCT10 Triple 3-input NAND gate Rev. 4 — 8 January 2021 Product data sheet 1. General description The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits Complies with JEDEC standard JESD7A Input levels: For74HC10: CMOS level For 74HCT10: TTL level Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74HC10D -40 °C to +125 °C 74HCT10D 74HC10PW -40 °C to +125 °C 74HCT10PW Name SO14 TSSOP14 Description plastic small outline package; 14 leads; body width 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT108-1 SOT402-1 4. Functional diagram 1 1A 2 1B 13 1C 3 2A 4 2B 5 2C 9 3A 10 3B 11 3C 1Y 12 2Y 6 3Y 8 mna757 Fig. 1. Logic symbol 1 2 & 12 13 3 4 & 6 5 9 10 & 8 11 mna759 Fig. 2. IEC logic symbol A B Y C mna758 Fig. 3. Logic diagram (one gate) Nexperia 5. Pinning information 74HC10; 74HCT10 Triple 3-input NAND gate 5.1. Pinning 74HC10 74HCT10 1A 1 1B 2 14 VCC 13 1C 2A 3 12 1Y 2B 4 11 3C 2C 5 10 3B 2Y 6 9 3A GND 7 8 3Y aaa-024297 Fig. 4. Pin configuration SOT108-1 (SO14) 74HC10 74...