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74HC137D Dataheets PDF



Part Number 74HC137D
Manufacturers nexperia
Logo nexperia
Description 3-to-8 line decoder/demultiplexer
Datasheet 74HC137D Datasheet74HC137D Datasheet (PDF)

74HC137 3-to-8 line decoder, demultiplexer with address latches; inverting Rev. 5 — 4 August 2021 Product data sheet 1. General description The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features a latch enable (LE) and two output enable (E1, E2) inputs. A LOW on LE causes the device to act as an active LOW decoder. A LOW-to HIGH transition on LE stores the data that was present before the transition in the.

  74HC137D   74HC137D


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74HC137 3-to-8 line decoder, demultiplexer with address latches; inverting Rev. 5 — 4 August 2021 Product data sheet 1. General description The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features a latch enable (LE) and two output enable (E1, E2) inputs. A LOW on LE causes the device to act as an active LOW decoder. A LOW-to HIGH transition on LE stores the data that was present before the transition in the latches. Further address changes are ignored as long as LE remains HIGH. The output enable inputs control the state of the outputs independently of the address inputs or latch operation. All outputs will be HIGH unless E1 is LOW and E2 is HIGH. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or independent controls • Active LOW mutually exclusive outputs • Wide supply voltage range from 2.0 to 6.0 V • CMOS low power dissipation • High noise immunity • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Complies with JEDEC standards • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 V to 6.0 V) • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • Specified from -40 °C to +80 °C and from -40 °C to +125 °C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74HC137D -40 °C to +125 °C Name SO16 74HC137DB -40 °C to +125 °C SSOP16 74HC137PW -40 °C to +125 °C TSSOP16 Description plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT109-1 SOT338-1 SOT403-1 Nexperia 74HC137 3-to-8 line decoder, demultiplexer with address latches; inverting 4. Functional diagram 1 A0 2 A1 3 A2 5 E1 6 E2 4 LE INPUT LATCHES 3 TO 8 DECODER Y0 15 Y1 14 Y2 13 Y3 12 Y4 11 Y5 10 Y6 9 Y7 7 Fig. 1. Functional diagram 4 LE 1 A0 2 3 A1 INPUT LATCHES A2 E1 5 6 E2 Fig. 2. Logic symbol Y0 15 Y1 14 Y2 13 3 TO 8 Y3 12 DECODER Y4 11 Y5 10 Y6 9 Y7 7 001aab879 001aab881 DX 4 C8 10 2 3 8D,G 0 7 2 5 & 6 0 15 1 14 2 13 3 12 4 11 5 10 69 77 X/Y 4 C8 1 8D,1 2 8D,2 3 8D,4 5 & 6 EN 0 15 1 14 2 13 3 12 4 11 5 10 69 77 001aab880 Fig. 3. IEC logic symbol 74HC137 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 4 August 2021 © Nexperia B.V. 2021. All rights reserved 2 / 16 Nexperia A0 A1 A2 LE 74HC137 3-to-8 line decoder, demultiplexer with address latches; inverting A0 LATCH A0 Y0 LE LE Y1 A1 LATCH A1 LE LE Y2 A2 LATCH A2 Y3 LE LE Y4 Y5 Y6 E1 E2 Fig. 4. Logic diagram Y7 001aab882 5. Pinning information 5.1. Pinning 74HC137 A0 1 16 VCC A1 2 15 Y0 A2 3 14 Y1 LE 4 13 Y2 E1 5 12 Y3 E2 6 11 Y4 Y7 7 10 Y5 GND 8 9 Y6 001aab878 Fig. 5. Pin configuration SOT109-1 (SO16) 74HC137 A0 1 A1 2 A2 3 LE 4 E1 5 E2 6 Y7 7 GND 8 16 VCC 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 aaa-033060 Fig. 6. Pin configuration SOT338-1 (SSOP16) and SOT403-1 (TSSOP16) 74HC137 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 4 August 2021 © Nexperia B.V. 2021. All rights reserved 3 / 16 Nexperia 74HC137 3-to-8 line decoder, demultiplexer with address latches; inverting 5.2. Pin description Table 2. Pin description Symbol Pin A0 1 A1 2 A2 3 LE 4 E1 5 E2 6 Y7 7 GND 8 Y6 9 Y5 10 Y4 11 Y3 12 Y2 13 Y1 14 Y0 15 VCC 16 Description data input 0 data input 1 data input 2 latch enable input (active LOW) data enable input 1 (active LOW) data enable input 2 (active HIGH) multiplexer output 7 ground (0 V) multiplexer output 6 multiplexer output 5 multiplexer output 4 multiplexer output 3 multiplexer output 2 multiplexer output 1 multiplexer output 0 positive supply voltage 6. Function table Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care. Enable Input Output LE E1 E2 A0 A1 A2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 H L H X X X stable X H X X X X H H H H H H H H X X L X X X H H H H H H H H L L H L L L L H H H H H H H H L L H L H H H H H H L H L H H L H H H H H H H L H H H L H H H H L L H H H H H L H H H H L H H H H H H L H H L H H H H H H H H L H H H H H H H H H H H L 74HC137 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 4 August 2021 © Nexperia B.V. 2021. All rights reserved 4 / 16 Nexperia 74HC137 3-to-8 line decoder, demultiplexer with address latches; inverting 7. Limiting values Tabl.


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