Document
74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Rev. 5 — 9 August 2021
Product data sheet
1. General description
The 74HC166; 74HCT166 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and a serial output (Q7). When the parallel enable input (PE) is LOW, the data from D0 to D7 is loaded into the shift register on the next LOW-to-HIGH transition of the clock input (CP). When PE is HIGH, data enters the register serially at DS with each LOW-to-HIGH transition of CP. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of CP. A HIGH on CE disables the CP input. Inputs include clamp diodes which enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
• Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • High noise immunity • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Synchronous parallel-to-serial applications • Synchronous serial input for easy expansion • Input levels:
• For 74HC166: CMOS level • For 74HCT166: TTL level • Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 V to 6.0 V) • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information Type number Package
Temperature range Name 74HC166D -40 °C to +125 °C SO16 74HCT166D 74HC166PW -40 °C to +125 °C TSSOP16 74HCT166PW
Description
Version
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
Nexperia
74HC166; 74HCT166
8-bit parallel-in/serial out shift register
4. Functional diagram
15 1
PE DS
2 D0 3 D1 4 D2 5 D3 10 D4 11 D5 12 D6 14 D7
Q7 13
9 MR CP CE
76 aaa-008816
Fig. 1. Logic symbol
SRG8
6
7 ≥1 C1/2
15 9
M2 R
1 2,1D 2 2,1D 3 2,1D 4 5 10 11 12 14
Fig. 2. IEC logic symbol
13 aaa-008817
15 PE 1 DS
2 3 4 5 10 11 12 14 D0 D1 D2 D3 D4 D5 D6 D7
MR 9 7 CP 6 CE
8-BIT PARALLEL/SERIAL-IN/ SERIAL-OUT SHIFT REGISTER
Q7 13
Fig. 3. Functional diagram
aaa-008818
74HC_HCT166
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 August 2021
© Nexperia B.V. 2021. All rights reserved
2 / 17
Nexperia
PE DS
74HC166; 74HCT166
8-bit parallel-in/serial out shift register
D0
D1
D2
D3
D4
D5
D6
D7
CP CE MR
Fig. 4. Logic diagram
S
CP
FF 1
R RD
S
CP
FF 2
R RD
S
CP
FF 3
R RD
S
CP
FF 4
R RD
S
CP
FF 5
R RD
S
CP
FF 6
R RD
S
CP
FF 7
R RD
S
CP
FF 8
R RD
Q7
aaa-008819
74HC_HCT166
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 August 2021
© Nexperia B.V. 2021. All rights reserved
3 / 17
Nexperia
5. Pinning information
74HC166; 74HCT166
8-bit parallel-in/serial out shift register
5.1. Pinning
74HC166 74HCT166
DS 1
16 VCC
D0 2
15 PE
D1 3
14 D7
D2 4
13 Q7
D3 5
12 D6
CE 6
11 D5
CP 7
10 D4
GND 8
9 MR
aaa-033054
Fig. 5. Pin configuration for SOT109-1 (SO16)
74HC166 74HCT166
DS 1 D0 2 D1 3 D2 4 D3 5 CE 6 CP 7 GND 8
16 VCC 15 PE 14 D7 13 Q7 12 D6 11 D5 10 D4 9 MR
aaa-033055
Fig. 6. Pin configuration for SOT403-1 (TSSOP16)
5.2. Pin description
Table 2. Pin description Symbol DS D0 to D7 CE CP GND MR Q7 PE VCC
Pin 1 2, 3, 4, 5, 10, 11, 12, 14 6 7 8 9 13 15 16
Description serial data input parallel data inputs clock enable input (active LOW) clock input (LOW-to-HIGH edge-triggered) ground (0 V) asynchronous master reset (active LOW) serial output from the last stage parallel enable input (active LOW) positive supply voltage
74HC_HCT166
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 August 2021
© Nexperia B.V. 2021. All rights reserved
4 / 17
Nexperia
74HC166; 74HCT166
8-bit parallel-in/serial out shift register
6. Functional description
Table 3. Function table H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition; X = don’t care; ↑ = LOW-to-HIGH clock transition.
Operating modes Inputs
Qn registers
PE
CE
CP
DS
D0 to D7 Q0
Q1 to Q6
parallel load
I
I
↑
X
I
L
L to L
I
I
↑
X
h
H
H to H
serial shift
h
I
↑
l
X
L
q0 to q5
h
I
↑
h
X
H
q0 to q5
hold "do nothing"
X
H
X
X
X
q0
q1 to q6
Output Q7 L H q6 q6 q7
CP
mode
control
CE
inputs
MR
parallel inputs
DS shift/ load
D0 D1 D2 D3 D4 D5 D6
D7
output
Q7
serial shift
H L
H L
H L
H
H
HH L H L H L H
inhibit
ser.