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AD73422 Dataheets PDF



Part Number AD73422
Manufacturers Analog Devices
Logo Analog Devices
Description Dual Low Power CMOS Analog Front-End
Datasheet AD73422 DatasheetAD73422 Datasheet (PDF)

a Dual Low Power CMOS Analog Front End with DSP Microcomputer AD73422 FUNCTIONAL BLOCK DIAGRAM POWER-DOWN CONTROL DATA ADDRESS GENERATORS DAG 1 DAG 2 MEMORY 16K PM 16K DM (OPTIONAL (OPTIONAL 8K) 8K) FEATURES AFE PERFORMANCE Two 16-Bit A/D Converters Two 16-Bit D/A Converters Programmable Input/Output Sample Rates 78 dB ADC SNR 77 dB DAC SNR 64 kS/s Maximum Sample Rate –90 dB Crosstalk Low Group Delay (25 ␮s Typ per ADC Channel, 50 ␮s Typ per DAC Channel) Programmable Input/Output Gain On-Chip .

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a Dual Low Power CMOS Analog Front End with DSP Microcomputer AD73422 FUNCTIONAL BLOCK DIAGRAM POWER-DOWN CONTROL DATA ADDRESS GENERATORS DAG 1 DAG 2 MEMORY 16K PM 16K DM (OPTIONAL (OPTIONAL 8K) 8K) FEATURES AFE PERFORMANCE Two 16-Bit A/D Converters Two 16-Bit D/A Converters Programmable Input/Output Sample Rates 78 dB ADC SNR 77 dB DAC SNR 64 kS/s Maximum Sample Rate –90 dB Crosstalk Low Group Delay (25 ␮s Typ per ADC Channel, 50 ␮s Typ per DAC Channel) Programmable Input/Output Gain On-Chip Reference DSP PERFORMANCE 19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 400 Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode GENERAL DESCRIPTION FULL MEMORY MODE PROGRAMMABLE I/O AND FLAGS EXTERNAL ADDRESS BUS EXTERNAL DATA BUS BYTE DMA CONTROLLER OR EXTERNAL DATA BUS TIMER INTERNAL DMA PORT HOST MODE PROGRAM SEQUENCER PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA ARITHMETIC UNITS ALU MAC SHIFTER ADSP-2100 BASE ARCHITECTURE SERIAL PORTS SPORT 0 SPORT 1 REF SERIAL PORT SPORT 2 ADC1 DAC1 ADC2 DAC2 ANALOG FRONT END SECTION applications. The A/D and D/A conversion channels feature programmable input/output gains with ranges 38 dB and 21 dB respectively. An on-chip reference voltage is included to allow single supply operation. The sampling rate of the AFE is programmable with four separate settings offering 64, 32, 16 and 8 kHz sampling rates (from a master clock of 16.384 MHz), while the serial port (SPORT2) allows easy expansion of the number of I/O channels by cascading extra AFEs external to the AD73422. The AD73422’s DSP engine combines the ADSP-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities and on-chip program and data memory. The AD73422-80 integrates 80K bytes of on-chip memory configured as 16K words (24-bit) of program RAM, and 16K words (16-bit) of data RAM. The AD73422-40 integrates 40K bytes of on-chip memory configured as 8K words (24-bit) of program RAM, and 8K words (16-bit) of data RAM. Powerdown circuitry is also provided to meet the low power needs of battery operated portable equipment. The AD73422 is available in a 119-ball PBGA package. The AD73422 is a single device incorporating a dual analog front end and a microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The AD73422’s analog front end (AFE) section features a dual front-end converter for general purpose applications including speech and telephony. The AFE section features two 16-bit A/D conversion channels and two 16-bit D/A conversion channels. Each channel provides 77 dB signal-to-noise ratio over a voiceband signal bandwidth. It also features an input-to-output gain network in both the analog and digital domains. This is featured on both codecs and can be used for impedance matching or scaling when interfacing to Subscriber Line Interface Circuits (SLICs). The AD73422 is particularly suitable for a variety of applications in the speech and telephony area including low bit rate, high quality compression, speech enhancement, recognition and synthesis. The low group delay characteristic of the AFE makes it suitable for single or multichannel active control REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD73422–SPECIFICATIONS f Parameter AFE SECTION REFERENCE REFCAP Absolute Voltage, VREFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, VREFOUT Minimum Load Resistance Maximum Load Capacitance INPUT AMPLIFIER Offset Maximum Output Swing Feedback Resistance Feedback Capacitance ANALOG GAIN TAP Gain at Maximum Setting Gain at Minimum Setting Gain Resolution Gain Accuracy Settling Time Delay ADC SPECIFICATIONS Maximum Input Range at VIN2, 3 Nominal Reference Level at VIN (0 dBm0) Absolute Gain PGA = 0 dB PGA = 38 dB Gain Tracking Error Signal to (Noise + Distortion) PGA = 0 dB PGA = 38 dB Total Harmonic Distortion PGA = 0 dB PGA = 38 dB Intermodulation Distortion Idle Channel Noise Crosstalk, ADC-to-DAC ADC-to-ADC (AVDD = DVDD = VDD = +3 V to 3.6 V; DGND = AGND = 0 V, fDMCLK = 16..


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