DatasheetsPDF.com

74HC2G00DP

nexperia

Dual 2-input NAND gate

74HC2G00; 74HCT2G00 Dual 2-input NAND gate Rev. 6 — 20 November 2018 Product data sheet 1. General description The 74...


nexperia

74HC2G00DP

File DownloadDownload 74HC2G00DP Datasheet


Description
74HC2G00; 74HCT2G00 Dual 2-input NAND gate Rev. 6 — 20 November 2018 Product data sheet 1. General description The 74HC2G00; 74HCT2G00 is a dual 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V Input levels: For 74HC2G00: CMOS level For 74HCT2G00: TTL level Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays ESD protection: HBM JESD22-A114E exceeds 2 000 V MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74HC2G00DP -40 °C to +125 °C TSSOP8 74HCT2G00DP 74HC2G00DC -40 °C to +125 °C VSSOP8 74HCT2G00DC Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm Version SOT505-2 plastic very thin shrink small outline package; SOT765-1 8 leads; body width 2.3 mm 4. Marking Table 2. Marking code Type number 74HC2G00DP 74HCT2G00DP 74HC2G00DC 74HCT2G00DC Marking code[1] H00 T00 H00 T00 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. Nexperia 5. Functional diagram 1 1A 2 1B 5 2A 6 2B 1Y 7 2Y 3 mna712 Fig. 1. Logic symbol 1 & 7 2 5 & 3 6 mna713 Fig. 2. IEC logic symbol 6. Pinning information ...




Similar Datasheet




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)