Dual buffer gate
74HC2G16; 74HCT2G16
Dual buffer gate
Rev. 2 — 2 February 2022
Product data sheet
1. General description
The 74HC2G16;...
Description
74HC2G16; 74HCT2G16
Dual buffer gate
Rev. 2 — 2 February 2022
Product data sheet
1. General description
The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers.
2. Features and benefits
Wide supply voltage range from 2.0 V to 6.0 V High noise immunity CMOS low power dissipation Balanced propagation delays Unlimited input rise and fall times Complies with JEDEC standards:
JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: HBM JESD22-A114-D exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C and -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74HC2G16GW
-40 °C to +125 °C TSSOP6
74HCT2G16GW
74HC2G16GV 74HCT2G16GV
-40 °C to +125 °C
SC-74; TSOP6
Description plastic thin shrink small outline package; 6 leads; body width 1.25 mm
plastic surface-mounted package; 6 leads
Version SOT363-2
SOT457
4. Marking
Table 2. Marking Type number 74HC2G16GW 74HCT2G16GW 74HC2G16GV 74HCT2G16GV
Marking code[1] P6 U6 P6 U6
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
Nexperia
5. Functional diagram
74HC2G16; 74HCT2G16
Dual buffer gate
1 1A
1Y 6
3 2A
2Y 4
mnb063
Fig. 1. Logic symbol
1
1
6
3
1
4
mnb064
Fig. 2. IEC logic symbol
A
Y
001aac536
Fig. 3. Logic diagram (one gate)
6. Pinning information
6.1. Pinning
74HC2G16 74HCT2G16
1A 1
...
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