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74HCT4067D Dataheets PDF



Part Number 74HCT4067D
Manufacturers nexperia
Logo nexperia
Description 16-channel analog multiplexer/demultiplexer
Datasheet 74HCT4067D Datasheet74HCT4067D Datasheet (PDF)

74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer Rev. 8 — 9 September 2021 Product data sheet 1. General description The 74HC4067; 74HCT4067 is a single-pole 16-throw analog switch (SP16T) suitable for use in analog or digital 16:1 multiplexer/demultiplexer applications. The switch features four digital select inputs (S0, S1, S2 and S3), sixteen independent inputs/outputs (Yn), a common input/output (Z) and a digital enable input (E). When E is HIGH, the switches are turned of.

  74HCT4067D   74HCT4067D


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74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer Rev. 8 — 9 September 2021 Product data sheet 1. General description The 74HC4067; 74HCT4067 is a single-pole 16-throw analog switch (SP16T) suitable for use in analog or digital 16:1 multiplexer/demultiplexer applications. The switch features four digital select inputs (S0, S1, S2 and S3), sixteen independent inputs/outputs (Yn), a common input/output (Z) and a digital enable input (E). When E is HIGH, the switches are turned off. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Wide supply voltage range from 2.0 V to 10.0 V • Input levels S0, S1, S2, S3 and E inputs: • For 74HC4067: CMOS level • For 74HCT4067: TTL level • CMOS low power dissipation • High noise immunity • Low ON resistance: • 80 Ω (typical) at VCC = 4.5 V • 70 Ω (typical) at VCC = 6.0 V • 60 Ω (typical) at VCC = 9.0 V • Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 V to 6.0 V) • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22-C101E exceeds 1000 V • Multiple package options • Specified from -40 °C to +85 °C and -40 °C to +125 °C • Typical ‘break before make’ built-in 3. Applications • Analog multiplexing and demultiplexing • Digital multiplexing and demultiplexing • Signal gating Nexperia 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4067D 74HCT4067D -40 °C to +125 °C SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 74HC4067PW 74HCT4067PW -40 °C to +125 °C TSSOP24 plastic thin shrink small outline package; 24 leads; SOT355-1 body width 4.4 mm 74HC4067BQ 74HCT4067BQ -40 °C to +125 °C DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 × 5.5 × 0.85 mm SOT815-1 5. Functional diagram S0 10 S1 11 S2 14 S3 13 E 15 Fig. 1. Logic symbol 9 Y0 8 Y1 7 Y2 6 Y3 5 Y4 4 Y5 3 Y6 2 Y7 23 Y8 22 Y9 21 Y10 20 Y11 19 Y12 18 Y13 17 Y14 16 Y15 1 Z 001aag725 10 11 14 13 0 16 × 0 15 3 15 G16 Fig. 2. MUX/DMUX 09 18 27 1 36 45 54 63 72 8 23 9 22 10 21 11 20 12 19 13 18 14 17 15 16 001aag726 IEC logic symbol 74HC_HCT4067 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 9 September 2021 © Nexperia B.V. 2021. All rights reserved 2 / 25 Nexperia from logic Fig. 3. Schematic diagram (one switch) 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer Yn VCC VCC GND Z 001aag729 S0 10 S1 11 S2 14 S3 13 1-OF-16 DECODER E 15 Fig. 4. Functional diagram 9 Y0 8 Y1 7 Y2 6 Y3 5 Y4 4 Y5 3 Y6 2 Y7 23 Y8 22 Y9 21 Y10 20 Y11 19 Y12 18 Y13 17 Y14 16 Y15 1Z 001aag727 74HC_HCT4067 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 9 September 2021 © Nexperia B.V. 2021. All rights reserved 3 / 25 Nexperia S0 S1 S2 S3 E Fig. 5. Logic diagram 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Z 001aag728 74HC_HCT4067 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 9 September 2021 © Nexperia B.V. 2021. All rights reserved 4 / 25 Nexperia 6. Pinning information 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer 6.1. Pinning 74HC4067 74HCT4067 Z1 Y7 2 Y6 3 Y5 4 Y4 5 Y3 6 Y2 7 Y1 8 Y0 9 S0 10 S1 11 GND 12 24 VCC 23 Y8 22 Y9 21 Y10 20 Y11 19 Y12 18 Y13 17 Y14 16 Y15 15 E 14 S2 13 S3 001aag730 Fig. 6. Pin configuration SOT137-1 (SO24) and SOT355-1 (TSSOP24) terminal 1 index area 74HC4067 74HCT4067 1Z 24 VCC Y7 2 Y6 3 Y5 4 Y4 5 Y3 6 Y2 7 Y1 8 Y0 9 S0 10 S1 11 VCC(1) 23 Y8 22 Y9 21 Y10 20 Y11 19 Y12 18 Y13 17 Y14 16 Y15 15 E 14 S2 GND 12 S3 13 001aag731 Fig. 7. Transparent top view (1) This is not a supply pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to VCC. Pin configuration SOT815-1 (DHVQFN24) 6.2. Pin description Table 2. Pin description Symbol Z Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0, Y15, Y14, Y13, Y12, Y11, Y10, Y9, Y8 S0, S1, S2, S3 GND E VCC Pin 1 2, 3, 4, 5, 6, 7, 8, 9, 16, 17, 18, 19, 20, 21, 22, 23 10, 11, 14, 13 12 15 24 Description common input or output independent input or output address input ground (0 V) enable input (active LOW) supply voltage 74HC_HCT4067 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 9 September 2021 © Nexperia B.V. 2021. All rights reserved 5 / 25 Nexperia 7.


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