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74HC4094PW Dataheets PDF



Part Number 74HC4094PW
Manufacturers nexperia
Logo nexperia
Description 8-stage shift-and-store bus register
Datasheet 74HC4094PW Datasheet74HC4094PW Datasheet (PDF)

74HC4094; 74HCT4094 8-stage shift-and-store bus register Rev. 9 — 22 October 2021 Product data sheet 1. General description The 74HC4094; 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 o.

  74HC4094PW   74HC4094PW



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74HC4094; 74HCT4094 8-stage shift-and-store bus register Rev. 9 — 22 October 2021 Product data sheet 1. General description The 74HC4094; 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-toHIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH. Data in the storage register appears at the outputs whenever the output enable input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Complies with JEDEC standard JESD7A • Input levels: • For 74HC4094: CMOS level • For 74HCT4094: TTL level • Low-power dissipation • ESD protection: • • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Applications • Serial-to-parallel data conversion • Remote control holding register 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description 74HC4094D 74HCT4094D -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm 74HCT4094DB -40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm 74HC4094PW 74HCT4094PW -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT109-1 SOT338-1 SOT403-1 Nexperia 5. Functional diagram 3 1 CP STR QS1 9 QS2 10 QP0 4 QP1 5 2D QP2 6 QP3 7 QP4 14 QP5 13 QP6 12 QP7 11 OE Fig. 1. Logic symbol 15 001aaf111 2D 3 CP 1 STR 74HC4094; 74HCT4094 8-stage shift-and-store bus register 1 C2 15 EN3 SRG8 3 C1/ 2 1D 2D 3 4 5 6 7 14 13 12 11 9 10 Fig. 2. IEC Logic symbol 001aaf112 8-STAGE SHIFT REGISTER 8-BIT STORAGE REGISTER QS2 10 QS1 9 15 OE 3-STATE OUTPUTS QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7 Fig. 3. Functional diagram STAGE 0 D DQ CP FF 0 CP DQ LE LATCH 0 STR 4 5 6 7 14 13 12 11 001aaf119 STAGES 1 TO 6 D Q CP STAGE 7 DQ CP FF 7 DQ LE LATCH 7 QS1 DQ LE LATCH QS2 OE Fig. 4. Logic diagram 74HC_HCT4094 Product data sheet QP0 QP2 QP4 QP6 QP1 QP3 QP5 QP7 001aag799 All information provided in this document is subject to legal disclaimers. Rev. 9 — 22 October 2021 © Nexperia B.V. 2021. All rights reserved 2 / 19 Nexperia 6. .


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