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74HC574D Dataheets PDF



Part Number 74HC574D
Manufacturers nexperia
Logo nexperia
Description Octal D-type flip-flop
Datasheet 74HC574D Datasheet74HC574D Datasheet (PDF)

74HC574; 74HCT574 Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 9 — 20 October 2022 Product data sheet 1. General description The 74HC574; 74HCT574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assum.

  74HC574D   74HC574D


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74HC574; 74HCT574 Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 9 — 20 October 2022 Product data sheet 1. General description The 74HC574; 74HCT574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • High noise immunity • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 V to 6.0 V) • Input levels: • For 74HC574: CMOS level • For 74HCT574: TTL level • 3-state non-inverting outputs for bus oriented applications • 8-bit positive, edge-triggered register • Common 3-state output enable input • ESD protection: • • HBM JESD22-A114F exceeds 2 kV • MM JESD22-A115-A exceeds 200 V • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74HC574D 74HCT574D -40 °C to +125 °C 74HC574PW 74HCT574PW -40 °C to +125 °C 74HC574BQ -40 °C to +125 °C Name SO20 TSSOP20 DHVQFN20 Description plastic small outline package; 20 leads; body width 7.5 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm Version SOT163-1 SOT360-1 SOT764-1 Nexperia 4. Functional diagram 74HC574; 74HCT574 Octal D-type flip-flop; positive edge-trigger; 3-state 2 D0 3 D1 4 D2 5 D3 FF1 6 D4 to FF8 7 D5 8 D6 9 D7 3-STATE OUTPUTS Q0 19 Q1 18 Q2 17 Q3 16 Q4 15 Q5 14 Q6 13 Q7 12 11 CP 1 OE mna800 Fig. 1. Functional diagram D0 D1 D2 D3 D4 D5 D6 D7 DQ CP DQ CP DQ CP DQ CP DQ CP DQ CP DQ CP DQ CP FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8 CP OE Q0 Q1 Fig. 2. Logic diagram 11 CP 2 D0 Q0 19 3 D1 Q1 18 4 D2 Q2 17 5 D3 Q3 16 6 D4 Q4 15 7 D5 Q5 14 8 D6 Q6 13 9 D7 Q7 12 OE 1 mna798 Fig. 3. Logic symbol Q2 Q3 Q4 Q5 Q6 Q7 001aah077 11 C1 1 EN 2 1D 3 4 5 6 7 8 9 Fig. 4. IEC logic symbol 19 18 17 16 15 14 13 12 mna446 74HC_HCT574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 20 October 2022 © Nexperia B.V. 2022. All rights reserved 2 / 17 Nexperia 5. Pinning information 74HC574; 74HCT574 Octal D-type flip-flop; positive edge-trigger; 3-state 5.1. Pinning D package SOT163-1 (SO20) OE 1 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 GND 10 20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 CP aaa-035109 BQ package SOT764-1 (DHVQFN20) 1 OE 20 VCC PW package SOT360-1 (TSSOP20) OE 1 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 GND 10 20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 CP terminal 1 index area D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 GND(1) 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 aaa-035111 GND 10 CP 11 aaa-035110 Transparent top view (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. 5.2. Pin description Table 2. Pin description Symbol OE D0, D1, D2, D3, D4, D5, D6, D7 GND CP Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 VCC Pin 1 2, 3, 4, 5, 6, 7, 8, 9 10 11 19, 18, 17, 16, 15, 14, 13, 12 20 Description 3-state output enable input (active LOW) data inputs ground (0 V) clock input (LOW-to-HIGH, edge triggered) 3-state flip-flop outputs supply voltage 74HC_HCT574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 20 October 2022 © Nexperia B.V. 2022. All rights reserved 3 / 17 Nexperia 74HC574; 74HCT574 Octal D-type flip-flop; positive edge-trigger; 3-state 6. Functional description Table 3. Function table H = HIGH voltage level; h = HIGH voltage level one setup time prior to the HIGH-to-LOW CP transition; L = LOW voltage level; l = LOW voltage level one setup time prior to the HIGH-to-LOW CP transition; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH clock transition. Operating mode Input Internal OE CP Dn flip-flop Load and read register L ↑ l L L ↑ h H Load register and disable output H ↑ l L H ↑ h H Output Qn L H Z Z 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol.


74HCT573D 74HC574D 74HCT574D


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