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74HC597D Dataheets PDF



Part Number 74HC597D
Manufacturers nexperia
Logo nexperia
Description 8-bit shift register
Datasheet 74HC597D Datasheet74HC597D Datasheet (PDF)

74HC597; 74HCT597 8-bit shift register with input flip-flops Rev. 5 — 26 October 2021 Product data sheet 1. General description The 74HC597; 74HCT597 is an 8-bit shift register with input flip-flops. It consists of an 8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and the shift register have positive edge-triggered clocks. The shift register also has direct load (from storage) and clear inputs. Inputs include clamp diodes that enable th.

  74HC597D   74HC597D


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74HC597; 74HCT597 8-bit shift register with input flip-flops Rev. 5 — 26 October 2021 Product data sheet 1. General description The 74HC597; 74HCT597 is an 8-bit shift register with input flip-flops. It consists of an 8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and the shift register have positive edge-triggered clocks. The shift register also has direct load (from storage) and clear inputs. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • High noise immunity • Input levels: • For 74HC597: CMOS level • For 74HCT597: TTL level • 8-bit parallel storage register inputs • Shift register has direct overriding load and clear • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Complies with JEDEC standards • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 V to 6.0 V) • ESD protection: • • HBM EIA/JESD22-A114F exceeds 2000 V • MM EIA/JESD22-A115-A exceeds 200 V • Multiple package options • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74HC597D -40 °C to +125 °C SO16 74HCT597D 74HCT597DB -40 °C to +125 °C SSOP16 74HC597PW -40 °C to +125 °C 74HCT597PW TSSOP16 Description plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT109-1 SOT338-1 SOT403-1 Nexperia 74HC597; 74HCT597 8-bit shift register with input flip-flops 4. Functional diagram STCP 12 D0 15 D1 1 D2 2 D3 3 D4 4 INPUT FLIP-FLOPS D5 5 D6 6 D7 7 Fig. 1. Functional diagram MR DS 10 14 8-BIT SHIFT REGISTER 9Q 13 11 PL SHCP aaa-012057 10 11 13 12 C1 14 1 15 1D 1 1D 2 3 4 5 6 7 Fig. 3. IEC Logic symbol STCP D0 15 12 D1 1 D2 2 D3 3 INPUT FLIP- D4 4 FLOPS D5 5 D6 6 D7 7 Fig. 2. Logic symbol R SRG8 C3/ C2 3D 2D 2D 9 aaa-012055 MR DS 10 14 8-BIT SHIFT REGISTER 13 11 9 Q PL SHCP aaa-012056 74HC_HCT597 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 2 / 20 Nexperia MR SHCP PL STCP DS D0 1D C1 D1 1D C1 D2 1D C1 D3 1D C1 D4 1D C1 D5 1D C1 D6 1D C1 D7 1D C1 Fig. 4. Logic diagram 74HC597; 74HCT597 8-bit shift register with input flip-flops C2 S 2D R C3 3S S 3R R C3 3S S 3R R C3 3S S 3R R C3 3S S 3R R C3 3S S 3R R C3 3S S 3R R C3 3S S 3R R Q aaa-012058 74HC_HCT597 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 3 / 20 Nexperia 5. Pinning information 74HC597; 74HCT597 8-bit shift register with input flip-flops 5.1. Pinning 74HC597 74HCT597 D1 1 16 VCC D2 2 15 D0 D3 3 14 DS D4 4 13 PL D5 5 12 STCP D6 6 11 SHCP D7 7 10 MR GND 8 9Q aaa-012939 Fig. 5. Pin configuration SOT109-1 (SO16) 74HC597 74HCT597 D1 1 D2 2 D3 3 D4 4 D5 5 D6 6 D7 7 GND 8 16 VCC 15 D0 14 DS 13 PL 12 STCP 11 SHCP 10 MR 9Q aaa-012054 Fig. 6. Pin configuration SOT338-1 (SSOP16) and SOT403-1 (TSSOP16) 5.2. Pin description Table 2. Pin description Symbol GND Q MR SHCP STCP PL DS D0, D1, D2, D3, D4, D5, D6, D7 VCC Pin 8 9 10 11 12 13 14 15, 1, 2, 3, 4, 5, 6, 7 16 Description ground (0 V) serial data output asynchronous master reset input (active LOW) shift register clock input (LOW-to-HIGH, edge-triggered) storage register clock input (LOW-to-HIGH, edge-triggered) parallel load input (active LOW) serial data input parallel data inputs supply voltage 74HC_HCT597 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 4 / 20 Nexperia 74HC597; 74HCT597 8-bit shift register with input flip-flops 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition. Inputs Function STCP SHCP PL MR ↑ X X X data loaded to input latches ↑ X L H data loaded from inputs to shift register no clock edge X L H data transferred from input flip-flops to shift register X X L L invalid logic, state of shift register is indeterminate when signals removed X X H L shift register cleared X ↑ H H shift register clocked Qn = Qn-1, Q0 = DS SHCP DS MR PL STCP D0 H D1 L D2 H D3 L D4 H D5 H D6 L D7 H Q L LH L H reset shift register serial shift load input register parallel load shift register Fig. 7. Timing diagram L L L L L L L L L H L H L L H L H L H .


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