DatasheetsPDF.com

74LV74D Dataheets PDF



Part Number 74LV74D
Manufacturers nexperia
Logo nexperia
Description Dual D-type flip-flop
Datasheet 74LV74D Datasheet74LV74D Datasheet (PDF)

74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 5 — 24 March 2021 Product data sheet 1. General description The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the nQ output. Inputs include clamp .

  74LV74D   74LV74D


Document
74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 5 — 24 March 2021 Product data sheet 1. General description The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the nQ output. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. 2. Features and benefits • Wide supply voltage range from 1.0 V to 5.5 V • Optimized for low voltage applications from 1.0 V to 3.6 V • CMOS low power dissipation • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Direct interface with TTL levels (2.7 V to 3.6 V) • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74LV74D -40 °C to +125 °C 74LV74PW -40 °C to +125 °C Name Description Version SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 Nexperia 74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger 4. Functional diagram 4 10 1SD 2SD SD 2 12 1D 2D D Q 1Q 2Q 5 9 3 1CP CP FF 11 2CP Q 1Q 6 RD 2Q 8 1RD 2RD 1 13 aaa-008836 Fig. 1. Logic symbol 4 S 3 C1 2 1D 1 R 10 S 11 C2 12 2D 13 R Fig. 2. IEC logic symbol 4 1SD 2 1D SD D Q 1Q 5 3 1CP CP FF1 1 1RD 10 2SD Q 1Q 6 RD SD 12 2D D Q 2Q 9 11 2CP CP FF2 13 2RD Q 2Q 8 RD 5 6 9 8 aaa-008837 Fig. 3. Functional diagram aaa-008838 74LV74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 March 2021 © Nexperia B.V. 2021. All rights reserved 2 / 15 Nexperia 74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger Q C C C C D C RD SD CP C C Fig. 4. Logic diagram (one flip-flop) 5. Pinning information C C Q C aaa-008839 5.1. Pinning 74LV74 1RD 1 1D 2 14 VCC 13 2RD 1CP 3 12 2D 1SD 4 11 2CP 1Q 5 10 2SD 1Q 6 9 2Q GND 7 8 2Q aaa-008835 Fig. 5. Pin configuration SOT108-1 (SO14) 74LV74 1RD 1 1D 2 1CP 3 1SD 4 1Q 5 1Q 6 GND 7 14 VCC 13 2RD 12 2D 11 2CP 10 2SD 9 2Q 8 2Q aaa-033316 Fig. 6. Pin configuration SOT402-1 (TSSOP14) 5.2. Pin description Table 2. Pin description Symbol Pin 1RD, 2RD 1, 13 1D, 2D 2, 12 1CP, 2CP 3, 11 1SD, 2SD 4, 10 1Q, 2Q 5, 9 1Q, 2Q 6, 8 GND 7 VCC 14 Description asynchronous reset-direct input (active-LOW) data inputs clock input (LOW-to-HIGH), edge-triggered) asynchronous set-direct input (active-LOW) true flip-flop outputs complement flip-flop outputs ground (0 V) supply voltage 74LV74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 March 2021 © Nexperia B.V. 2021. All rights reserved 3 / 15 Nexperia 74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition; Qn+1 = state after the next LOW-to-HIGH CP transition Input Output nSD nRD nCP nD nQ nQ L H X X H L H L X X L H L L X X H H H H ↑ L - - H H ↑ H - - Qn+1 L H nQ n+1 H L 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions Min Max Unit VCC IIK VI IOK IO ICC IGND Tstg Ptot supply voltage input clamping current input voltage output clamping current output current supply current ground current storage temperature total power dissipation VI < -0.5 V or VI > VCC + 0.5 V VO > VCC or VO < 0 -0.5 V < VO < VCC + 0.5 V Tamb = -40 °C to +125 °C [1] -0.5 - [1] -0.5 - - - - -65 [2] - +7 V 20 mA +7 V ±50 mA ±25 mA ±50 mA ±50 mA +150 °C 500 [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C. For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. 74LV74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 March 2021 © Nexperia B.V. 2021. All rights reserved 4 / 15 Nexperia 74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC VI VO Tamb Δt/ΔV supply v.


74LV595D 74LV74D 74LV86


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)