DatasheetsPDF.com

74LV86 Dataheets PDF



Part Number 74LV86
Manufacturers nexperia
Logo nexperia
Description Quad 2-input exclusive-OR gate
Datasheet 74LV86 Datasheet74LV86 Datasheet (PDF)

74LV86 Quad 2-input exclusive-OR gate Rev. 03 — 27 November 2007 Product data sheet 1. General description The 74LV86 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC86 and 74HCT86. The 74LV86 provides a quad 2-input exclusive-OR function. 2. Features s Wide operating voltage: 1.0 V to 5.5 V s Optimized for low voltage applications: 1.0 V to 3.6 V s Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V s Typical output ground bounce < 0.8 V at VCC = 3..

  74LV86   74LV86



Document
74LV86 Quad 2-input exclusive-OR gate Rev. 03 — 27 November 2007 Product data sheet 1. General description The 74LV86 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC86 and 74HCT86. The 74LV86 provides a quad 2-input exclusive-OR function. 2. Features s Wide operating voltage: 1.0 V to 5.5 V s Optimized for low voltage applications: 1.0 V to 3.6 V s Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V s Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C s Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C s ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A115-A exceeds 200 V s Multiple package options s Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description 74LV86N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) 74LV86D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm 74LV86DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm 74LV86PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm 74LV86BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm Version SOT27-1 SOT108-1 SOT337-1 SOT402-1 SOT762-1 NXP Semiconductors 4. Functional diagram 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B Fig 1. Logic symbol 1Y 3 2Y 6 3Y 8 4Y 11 mna787 74LV86 Quad 2-input exclusive-OR gate 1 =1 3 2 4 =1 6 5 9 =1 8 10 12 =1 11 13 mna786 Fig 2. IEC logic symbol A B Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning Y mna788 1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7 14 VCC 13 4B 12 4A 86 11 4Y 10 3B 9 3A 8 3Y 001aad103 terminal 1 index area 1B 2 1Y 3 2A 4 2B 5 2Y 6 74LV86 1 1A 14 VCC VCC(1) 13 4B 12 4A 11 4Y 10 3B 9 3A GND 7 3Y 8 001aah098 Transparent top view Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration DHVQFN14 74LV86_3 Product data sheet Rev. 03 — 27 November 2007 © NXP B.V. 2007. All rights reserved. 2 of 15 NXP Semiconductors 74LV86 Quad 2-input exclusive-OR gate 5.2 Pin description Table 2. Symbol 1A 1B 1Y 2A 2B 2Y GND 3Y 3A 3B 4Y 4A 4B VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description data input data input data output data input data input data output ground (0 V) data output data input data input data output data input data input supply voltage 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level Input nA nB L L L H H L H H 7. Limiting values Output nY L H H L Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC IIK IOK IO ICC IGND Tstg supply voltage input clamping current output clamping current output current supply current ground current storage temperature VI < −0.5 V or VI > VCC + 0.5 V VO < −0.5 V or VO > VCC + 0.5 V VO = −0.5 V to (VCC + 0.5 V) −0.5 [1] [1] - −50 −65 +7.0 V ±20 mA ±50 mA ±25 mA 50 mA - mA +150 °C 74LV86_3 Product data sheet Rev. 03 — 27 November 2007 © NXP B.V. 2007. All rights reserved. 3 of 15 NXP Semiconductors 74LV86 Quad 2-input exclusive-OR gate Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit Ptot total power dissipation DIP14 package Tamb = −40 °C to +125 °C [2] - 750 mW SO14 package [3] - 500 mW (T)SSOP14 package [4] - 500 mW DHVQFN14 package [5] - 500 mW [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 12 mW/K above 70 °C. [3] Ptot derates linearly with 8 mW/K above 70 °C. [4] Ptot derates linearly with 5.5 mW/K above 60 °C. [5] Ptot derates linearly with 4.5 mW/K above 60 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC VI VO Tamb ∆t/∆V supply voltage[1] input voltage output voltage ambient temperature input transition rise and fall rate VCC = 1.0 V to 2.0 V VCC = 2.0 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 3.6 V to 5.5 V Min Typ Max Unit 1.0 3.3 5.5 V 0 - VCC V 0 - VCC V −40 +25 +125 °C - - 500 ns/V - - 200 ns/V - - 100 ns/V - - 50 ns/V [1] The static characteristics are guaranteed from .


74LV74D 74LV86 74LV86N


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)