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74LVT2245; 74LVTH2245
3.3 V octal transceiver with 30 Ω termination resistors; 3-state
Rev. 5 — 10 April 2017
Product data sheet
1 General description
The 74LVT2245; 74LVTH2245 is a high-performance BiCMOS product designed for VCC operation at 3.3 V.
This device is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The control function implementation minimizes external timing requirements. The device features an output enable input (OE) for easy cascading and a direction input (DIR) for direction control.
The 74LVT2245; 74LVTH2245 is designed with 30 Ω series resistance in both the HIGHstate and LOW-state of the output. This design reduces line noise in applications such as memory address drivers, clock drivers and bus transceivers and transmitters.
2 Features and benefits
• 30 Ω output termination resistors • Octal bidirectional bus interface • 3-state buffers • Output capability: +12 mA and -12 mA • TTL input and output switching levels • Input and output interface capability to systems at 5 V supply • Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs • Live insertion and extraction permitted • Power-up 3-state • No bus current loading when output is tied to 5 V bus • Latch-up protection:
– JESD78: exceeds 500 mA • ESD protection:
– MIL STD 883 method 3015: exceeds 2000 V – MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
Nexperia
74LVT2245; 74LVTH2245
3.3 V octal transceiver with 30 Ω termination resistors; 3-state
3 Ordering information
Table 1. Ordering information Type number Package
Temperature range
74LVT2245D
-40 °C to +85 °C
74LVTH2245D
74LVT2245DB
-40 °C to +85 °C
74LVTH2245DB
74LVT2245PW
-40 °C to +85 °C
74LVTH2245PW
Name
Description
Version
SO20
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
SSOP20
plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
TSSOP20 plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm
4 Functional diagram
DIR 1 A0 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9
Figure 1. Logic symbol
19 OE 18 B0 17 B1 16 B2 15 B3 14 B4 13 B5 12 B6 11 B7 mna817
19
G3
3 EN1 (BA)
1
3 EN2 (AB)
2 1
18
2
3
17
4
16
5
15
6
14
7
13
8
12
9
11
mna818
Figure 2. IEC logic symbol
VCC
VCC
25 Ω 25 Ω
mna819
Figure 3. Schematic of one output
74LVT_LVTH2245
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 April 2017
© Nexperia B.V. 2017. All rights reserved.
2 / 15
Nexperia
74LVT2245; 74LVTH2245
3.3 V octal transceiver with 30 Ω termination resistors; 3-state
5 Pinning information
5.1 Pinning
74LVT2245 75LVTH2245
DIR 1 A0 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 GND 10
20 VCC 19 OE 18 B0 17 B1 16 B2 15 B3 14 B4 13 B5 12 B6 11 B7
aaa-026622
Figure 4. Pin configuration for SO20
74LVT2245 74LVTH2245
DIR 1 A0 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 GND 10
20 VCC 19 OE 18 B0 17 B1 16 B2 15 B3 14 B4 13 B5 12 B6 11 B7
001aae465
Figure 5. Pin configuration for SSOP20 and TSSOP20
5.2 Pin description
Table 2. Pin description Symbol DIR A0, A1, A2, A3, A4, A5, A6, A7 GND B7, B6, B5, B4, B3, B2, B1, B0 OE VCC
Pin 1 2, 3, 4, 5, 6, 7, 8, 9 10 11, 12, 13, 14, 15, 16, 17, 18 19 20
6 Functional description
Table 3. Function table [1] Control
OE
DIR
L
L
L
H
H
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Input/output An output An = Bn input Z
Description direction control input data input/output ground (0 V) data input/output output enable input supply voltage
Bn input output Bn = An Z
74LVT_LVTH2245
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 April 2017
© Nexperia B.V. 2017. All rights reserved.
3 / 15
Nexperia
74LVT2245; 74LVTH2245
3.3 V octal transceiver with 30 Ω termination resistors; 3-state
7 Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max Unit
VCC
supply voltage
VI
input voltage
VO
output voltage
output in OFF-state or HIGH-state
IIK
input clamping current VI < 0 V
IOK
output clamping current VO < 0 V
IO
output current
output in LOW-state
output in HIGH-state
-0.5
[1]
-0.5
[1]
-0.5
-50
-50
-
-64
+4.6 V
+7.0 V
+7.0 V
-
mA
-
mA
128 mA
-
mA
Tstg
storage temperature
Tj
junction temperature
Ptot
total power dissipation Tamb = -40 to +85 °C
-65
[2]
-
[3]
+150 °C 150 °C 500 mW
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which
a.