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74LVC11PW Dataheets PDF



Part Number 74LVC11PW
Manufacturers nexperia
Logo nexperia
Description Triple 3-input AND gate
Datasheet 74LVC11PW Datasheet74LVC11PW Datasheet (PDF)

74LVC11 Triple 3-input AND gate Rev. 8 — 13 January 2020 Product data sheet 1. General description The 74LVC11 provides three 3-input AND functions. 2. Features and benefits • Wide supply voltage range from 1.2 V to 3.6 V • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct interface with TTL levels • Complies with JEDEC standard: • JESD8-7A (1.65 V to 1.95 V) • JESD8-5A (2.3 V to 2.7 V) • JESD8-C/JESD36 (2.7 V to 3.6 V) • ESD protection: • HBM JESD22-A114F exceeds 2000 .

  74LVC11PW   74LVC11PW



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74LVC11 Triple 3-input AND gate Rev. 8 — 13 January 2020 Product data sheet 1. General description The 74LVC11 provides three 3-input AND functions. 2. Features and benefits • Wide supply voltage range from 1.2 V to 3.6 V • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct interface with TTL levels • Complies with JEDEC standard: • JESD8-7A (1.65 V to 1.95 V) • JESD8-5A (2.3 V to 2.7 V) • JESD8-C/JESD36 (2.7 V to 3.6 V) • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-B exceeds 200 V • CDM JESD22-C101E exceeds 1000 V • Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description 74LVC11D -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm 74LVC11PW -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm 74LVC11BQ -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm Version SOT108-1 SOT402-1 SOT762-1 Nexperia 4. Functional diagram 1 1A 2 1B 13 1C 3 2A 4 2B 5 2C 9 3A 10 3B 11 3C 1Y 12 2Y 6 3Y 8 mna793 Fig. 1. Logic symbol 1 2 & 12 13 3 4 & 6 5 9 10 & 8 11 mna792 Fig. 2. IEC logic symbol 5. Pinning information 74LVC11 Triple 3-input AND gate A B Y C mna794 Fig. 3. Logic diagram for one gate 5.1. Pinning 74LVC11 1A 1 1B 2 14 VCC 13 1C 2A 3 12 1Y 2B 4 11 3C 2C 5 10 3B 2Y 6 9 3A GND 7 8 3Y 001aad043 Fig. 4. Pin configuration for SOT108-1 (SO14) 74LVC11 1A 1 1B 2 2A 3 2B 4 2C 5 2Y 6 GND 7 14 VCC 13 1C 12 1Y 11 3C 10 3B 9 3A 8 3Y aaa-027674 Fig. 5. Pin configuration for SOT337-1 (SSOP14) and SOT402-1 (TSSOP14) 74LVC11 1 1A 14 VCC terminal 1 index area 1B 2 2A 3 2B 4 2C 5 2Y 6 GND(1) 13 1C 12 1Y 11 3C 10 3B 9 3A GND 7 3Y 8 001aad044 Transparent top view (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. Fig. 6. Pin configuration for SOT762-1 (DHVQFN14) 74LVC11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 13 January 2020 © Nexperia B.V. 2020. All rights reserved 2 / 12 Nexperia 74LVC11 Triple 3-input AND gate 5.2. Pin description Table 2. Pin description Symbol 1A, 2A, 3A 1B, 2B, 3B 1C, 2C, 3C 1Y, 2Y, 3Y GND VCC Pin 1, 3, 9 2, 4, 10 13, 5, 11 12, 6, 8 7 14 6. Functional description Table 3. Function selection H = HIGH voltage level; L = LOW voltage level; X = don’t care Input nA nB nC L X X X L X X X L H H H Description data input data input data input data output ground (0 V) supply voltage Output nY L L L H 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). .


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