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AD7396 Dataheets PDF



Part Number AD7396
Manufacturers Analog Devices
Logo Analog Devices
Description 3 V/ Parallel Input Dual 12-Bit /10-Bit DACs
Datasheet AD7396 DatasheetAD7396 Datasheet (PDF)

a FEATURES Micropower: 100 ␮ A/DAC 0.1 ␮A Typical Power Shutdown Single Supply +2.7 V to +5.5 V Operation Compact 1.1 mm Height TSSOP 24-Lead Package AD7396: 12-Bit Resolution AD7397: 10-Bit Resolution 0.9 LSB Differential Nonlinearity Error APPLICATIONS Automotive Output Span Voltage Portable Communications Digitally Controlled Calibration PC Peripherals LDA CS A/B DATA 12 3 V, Parallel Input Dual 12-Bit /10-Bit DACs AD7396/AD7397 FUNCTIONAL BLOCK DIAGRAM AD7396 DACA REGISTER VDD 12 12-BIT DAC.

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a FEATURES Micropower: 100 ␮ A/DAC 0.1 ␮A Typical Power Shutdown Single Supply +2.7 V to +5.5 V Operation Compact 1.1 mm Height TSSOP 24-Lead Package AD7396: 12-Bit Resolution AD7397: 10-Bit Resolution 0.9 LSB Differential Nonlinearity Error APPLICATIONS Automotive Output Span Voltage Portable Communications Digitally Controlled Calibration PC Peripherals LDA CS A/B DATA 12 3 V, Parallel Input Dual 12-Bit /10-Bit DACs AD7396/AD7397 FUNCTIONAL BLOCK DIAGRAM AD7396 DACA REGISTER VDD 12 12-BIT DACA VOUTA INPUTA REGISTER 1 INPUTB REGISTER 12 VREF LDB DACB REGISTER 12-BIT DACB VOUTB AGND DGND RS SHDN GENERAL DESCRIPTION The AD7396/AD7397 series of dual, 12-bit and 10-bit voltageoutput digital-to-analog converters are designed to operate from a single +3 V supply. Built using a CBCMOS process, these monolithic DACs offer the user low cost and ease of use in single supply +3 V systems. Operation is guaranteed over the supply voltage range of +2.7 V to +5.5 V, making this device ideal for battery operated applications. A 12-bit wide data latch loads with a 45 ns write time allowing interface to fast processors without wait states. The double buffered input structure allows the user to load the input registers one at a time, then a single load strobe tied to both LDA+LDB inputs will simultaneously update both DAC outputs. LDA and LDB can also be independently activated to immediately update their respective DAC registers. An address input (A/B) decodes DACA or DACB when the chip select CS input is strobed. Additionally, an asynchronous RS input sets the output to zero-scale at power on or upon user demand. Power shutdown to submicroamp levels is directly controlled by the active low SHDN pin. While in the power shutdown state register data can still be changed even though the output buffer is in an open circuit state. Upon return to the normal operating state the latest data loaded in the DAC register will establish the output voltage. Both parts are offered in the same pinout, allowing users to select the amount of resolution appropriate for their applications without circuit card changes. The AD7396/AD7397 are specified for operation over the extended industrial (–40°C to +85°C) temperature range. The AD7397AR is specified for the –40°C to +125°C automotive temperature range. AD7396/AD7397s are available in plastic DIP, and 24-lead SOIC packages. The AD7397ARU is available for ultracompact applications in a thin 1.1 mm height TSSOP 24-lead package. 1.0 0.8 0.6 0.4 VDD = +3V VREF = +2.5V DNL – LSB 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 0 512 1024 1536 2048 2560 CODE – Decimal 3072 3584 4096 TA = +25؇C, +85؇C, –55؇C SUPERIMPOSED Figure 1. DNL vs. Digital Code at Temperature REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 AD7396/AD7397–SPECIFICATIONS AD7396 12-BIT ELECTRICAL CHARACTERISTICS (@ V Parameter STATIC PERFORMANCE Resolution1 Relative Accuracy2 Relative Accuracy2 Differential Nonlinearity2 Differential Nonlinearity2 Zero-Scale Error Zero-Scale Error Full-Scale Voltage Error Full-Scale Voltage Error Full-Scale Tempco3 REFERENCE INPUT VREF Range Input Resistance Input Capacitance3 ANALOG OUTPUT Output Current (Source) Output Current (Sink) Capacitive Load3 LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance3 INTERFACE TIMING3, 5 Chip Select Write Width DAC Select Setup DAC Select Hold Data Setup Data Hold Load Setup Load Hold Load Pulsewidth Reset Pulsewidth AC CHARACTERISTICS Output Slew Rate Settling Time6 Shutdown Recovery Time DAC Glitch Digital Feedthrough Feedthrough SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current Shutdown Supply Current Power Dissipation Power Supply Sensitivity Symbol N INL INL DNL DNL VZSE VZSE VFSE VFSE TCVFS VREF RREF CREF IOUT IOUT CL VIL VIH IIL CIL tCS tAS tAH tDS tDH tLS tLH tLDW tRSW SR tS tSDR Q Q VOUT/VREF Data = 000H to FFFH to 000H To ± 0.1% of Full Scale Code 7FFH to 800H to 7FFH VREF = 1.5 VDC +1 V p-p, Data = 000H, f = 100 kHz DNL < ± 1 LSB VIL = 0 V, No Load SHDN = 0, VIL = 0 V, No Load VIL = 0 V, No Load ∆VDD = ± 5% Data = 800H, ∆VOUT = 5 LSB Data = 800H, ∆VOUT = 5 LSB No Oscillation REF IN = +2.5 V, –40؇C < TA < +85؇C, unless otherwise noted) +3 V ؎ 10% +5 V ؎ 10% Units 12 ± 1.75 ± 2.0 ± 0.9 ±1 4.0 8.0 ±8 ± 20 –45 0/VDD 2.5 5 1 3 100 0.5 VDD – 0.6 10 10 45 30 0 30 20 20 10 30 40 0.05 70 90 65 15 –63 2.7/5.5 125/200 0.1/1.5 600 0.006 12 ± 1.75 ± 2.0 ± 0.9 ±1 4.0 8.0 ±8 ± 20 –45 0/VDD 2.5 5 1 3 100 0.8 4.0 10 10 .


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