Document
DESCRIPTION
This document describes the specification for the F1951 Digital Step Attenuator. The F1951 is part of a family of Glitch-FreeTM DSAs optimized for the demanding requirements of communications Infrastructure. These devices are offered in a compact 4x4 QFN package with 50 Ω impedances for ease of integration into the radio system.
COMPETITIVE ADVANTAGE
Digital step attenuators are used in Receivers and Transmitters to provide gain control. The F1951 is a 6bit step attenuator optimized for these demanding applications. The silicon design has very low insertion loss and low distortion (+65 dBm IP3I.). The device has pinpoint accuracy and settles to final attenuation value within 400 nsec. Most importantly, the F1951 includes Renesas’ Glitch-FreeTM technology which results in less than 0.6 dB of overshoot ringing during MSB transitions. This is in stark contrast to competing DSAs that glitch as much as 10 dB during MSB transitions (see p.10).
Lowest insertion loss for best SNR
Glitch-FreeTM when transitioning – won’t damage PA or ADC
Extremely accurate with low distortion
Glitch-FreeTTMM
APPLICATIONS
• Base Station 2G, 3G, 4G, TDD radiocards • Repeaters and E911 systems • Digital Pre-Distortion • Point to Point Infrastructure • Public Safety Infrastructure • WIMAX Receivers and Transmitters • Military Systems, JTRS radios • RFID handheld and portable readers • Cable Infrastructure
PART# MATRIX
Part# F1951 F1950 F1952
Freq range (MHz)
100 - 5000
150 - 5000
100 – 4000
Resolution / Range (dB) 0.50 / 31.5
0.25 / 31.5
0.50 / 15.5
Control Serial Only Serial Only Serial Only
IL (dB) -1.2
-1.3
-0.9
Pinout HITT PE HITT
FEATURES
• Glitch-FreeTM, < 0.6 dB transient overshoot • Spurious Free Design • 3 V to 5.25 V supply • Attenuation Error < 0.2 dB @ 2 GHz • Low Insertion Loss < 1.2 dB @ 2 GHz • Excellent Linearity +65 dBm IP3I • Fast settling time, < 450 ns • Class 2 JEDEC ESD (> 2kV HBM) • Serial Interface 31.5 dB Range • Stable Integral Non-Linearity over temperature • 4x4 mm Thin QFN 24 pin package
BLOCK DIAGRAM
RF1
RF2
Bias
DEC
SPI
RSTb
VDD
SDI SDO CLK CSb
ORDERING INFORMATION
0.8 mm height package
Tape & Reel
F1951NBGI8
Green
Industrial Temp range
© 2021 Renesas Electronics Corporation
1
Sep 28, 2021
ABSOLUTE MAXIMUM RATINGS
VDD to GND D[5:0], DATA, CLK, CSb, SDO, RSTb RF Input Power (RF1, RF2) calibration and testing RF Input Power (RF1, RF2) continuous RF operation θJA (Junction – Ambient) θJC (Junction – Case) The Case is defined as the exposed paddle Operating Temperature Range (Case Temperature) Maximum Junction Temperature Storage Temperature Range Lead Temperature (soldering, 10s)
-0.3 V to +5.50V -0.3 V to 3.6 V +29 dBm +23 dBm +50 °C/W +3 °C/W TC = -40 °C to +100°C 140 °C -65 °C to +150 °C +260 °C
© 2021 Renesas Electronics Corporation
2
Sep 28, 2021
F1951 SPECIFICATION (31.5 dB Range)
Specifications apply at VDD = +3.3V, fRF = 2000MHz, TC= +25°C unless otherwise noted, EVKit losses are de-embedde.