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IDTF1910 Dataheets PDF



Part Number IDTF1910
Manufacturers Renesas
Logo Renesas
Description Digital Step Attenuator
Datasheet IDTF1910 DatasheetIDTF1910 Datasheet (PDF)

DESCRIPTION This document describes the specification for the F1950 Digital Step Attenuator. The F1950 is part of a family of Glitch-FreeTM DSAs optimized for the demanding requirements of communications Infrastructure. These devices are offered in a compact 4x4 QFN package with 50 Ω impedances for ease of integration into the radio system. COMPETITIVE ADVANTAGE Digital step attenuators are used in Receivers and Transmitters to provide gain control. The F1950 is a 7bit step attenuator optimize.

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DESCRIPTION This document describes the specification for the F1950 Digital Step Attenuator. The F1950 is part of a family of Glitch-FreeTM DSAs optimized for the demanding requirements of communications Infrastructure. These devices are offered in a compact 4x4 QFN package with 50 Ω impedances for ease of integration into the radio system. COMPETITIVE ADVANTAGE Digital step attenuators are used in Receivers and Transmitters to provide gain control. The F1950 is a 7bit step attenuator optimized for these demanding applications. The silicon design has very low insertion loss and low distortion (+65 dBm IP3I). The device has pinpoint accuracy and settles to final attenuation value within 400 ns. Most importantly, the F1950 includes Renesas’ Glitch-FreeTM technology which results in less than 0.6 dB of overshoot ringing during MSB transitions. This is in stark contrast to competing DSAs that glitch as much as 10 dB during MSB transitions (see p.10).  Lowest insertion loss for best SNR  Glitch-FreeTM when transitioning – won’t damage PA or ADC  Extremely accurate with low distortion Glitch-FreeTTMM APPLICATIONS  Base Station 2G, 3G, 4G, TDD radiocards  Repeaters and E911 systems  Digital Pre-Distortion  Point to Point Infrastructure  Public Safety Infrastructure  WIMAX Receivers and Transmitters  Military Systems, JTRS radios  RFID handheld and portable readers  Cable Infrastructure PART# MATRIX Part# F1950 F1951 F1952 Freq range Resolution Control IL / Range Parallel & 150 - 5000 0.25 / 31.75 -1.3 Serial 100 - 5000 0.50 / 31.5 Serial Only -1.2 100 – 4000 0.50 / 15.5 Serial Only -0.9 Pinout PE HITT HITT FEATURES  Glitch-FreeTM, < 0.6 dB transient overshoot  Spurious Free Design  3V to 5V supply  Attenuation Error < 0.3 dB @ 2 GHz  Low Insertion Loss < 1.3 dB @ 2 GHz  Excellent Linearity +65 dBm IP3I  Fast settling time, < 400 ns  Class 2 JEDEC ESD (> 2kV HBM)  Serial & Parallel Interface 31.75 dB Range  4 x 4 mm Thin QFN 24 pin package BLOCK DIAGRAM RF1 RF2 Bias DEC SPI VMODE VDD 7 D[6:0] CLK DATA LE ORDERING INFORMATION 0.8 mm height package Tape & Reel F1950NBGI8 RF product Line Green Industrial Temp range Glitch-FreeTM Digital Step Attenuator 1 Rev 3 Aug 8, 2020 ABSOLUTE MAXIMUM RATINGS VDD to GND D[6:0], DATA, CLK, LE, VMODE RF Input Power (RF1, RF2) calibration and testing RF Input Power (RF1, RF2) continuous RF operation θJA (Junction – Ambient) θJC (Junction – Case) The Case is defined as the exposed paddle Operating Temperature Range (Case Temperature) Maximum Junction Temperature Storage Temperature Range Lead Temperature (soldering, 10s) -0.3 V to +5.5 V -0.3 V to 3.6 V +29 dBm +23 dBm +50 °C/W +3 °C/W TC = -40 °C to +100 °C 140 °C -65 °C to +150 °C +260 °C Glitch-FreeTM Digital Step Attenuator 2 Rev 3 Aug 8, 2020 F1950 SPECIFICATION (31.75 dB Range) Specifications apply at VDD = +3.3V, fRF = 2000MHz, and TC= +25°C, EVkit losses are de-embedded (see p. 17) for spec purposes Parameter Logic Input High Logic Input Low Logic Current Supply Voltage(s) Supply Current Temperature Range Frequency Range RF1, RF2 Return Loss Minimum Attenuation Maximum Attenuation Minimum Gain Step Phase Delta Differential Non-Linearity Integral Non-Linearity Integral Non-Linearity Comment CLK, LE, DATA, D[6:0], VMODE CLK, LE, DATA, D[6:0], VMODE VMODE Main Supply Total Operating Range (Case) Operating Range dB(s11), dB(s22) D[6:0] = [0000000] D[6:0] = [1111111] Least Significant Bit Phase change AMIN vs. AMAX Max error between adjacent steps Max Error vs. line (AMIN ref) to 13.75 dB ATTN Max Error vs. line (AMIN ref) to 31.75 dB ATTN Sym. VIH VIL IIH, IIL VDD IDD TC FRF S11, S22 AMIN or IL AMAX LSB ΦΔ DNL INL1 INL2 Min 2.3 -5 3.0 -40 150 32.6 Typical 3.30 0.25 -22 1.3 33.0 0.25 34 0.10 0.02 0.27 Max 3.6 0.7 +5 5.25 0.51 +100 5000 1.9 0.30 0.45 Units V V μA V mA °C MHz dB dB dB dB deg dB dB dB Input IP3 0.1 dB Compression Please note ABS MAX Input power on Page 2 Settling Time Serial Clock Speed Parallel to Serial Setup Serial Data Hold Time LE delay from final serial clock rising edge D[6:0] = [0000000] = AMIN D[6:0] = [0111111] = A15.75 D[6:0] = [1111111] = AMAX  PIN = +10 dBm per tone  50 MHz Tone Separation  D[6:0] = [0001010] = A2.5  Baseline PIN = 20 dBm  Start LE rising edge > VIH  End +/-0.10 dB Pout settling  15.75 – 16.00 transition SPI 3 wire bus SPI 3 wire bus SPI 3 wire bus SPI 3 wire bus IP3I1 IP3I2 IP3I3 P0.1 TLSB FCLK A B C +602 +59 +57 100 10 10 +63 +61 +61 27.5 400 20 dBm dBm ns 50 MHz ns ns ns SPECIFICATION NOTES: 1 – Items in min/max columns in bold italics are Guaranteed by Test 2 – All other Items in min/max columns are Guaranteed by Design Characterization Glitch-FreeTM Digital Step Attenuator 3 Rev 3 Aug 8, 2020 SERIAL CONTROL MODE Serial mode is selected by floating VMODE (pin3) or pulling it to a voltage > VI.


F1950NBGI8 IDTF1910 IDTF1950NBGI8


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