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IDT72V3631 Dataheets PDF



Part Number IDT72V3631
Manufacturers Renesas
Logo Renesas
Description 3.3 VOLT CMOS FIFO
Datasheet IDT72V3631 DatasheetIDT72V3631 Datasheet (PDF)

3.3 VOLT CMOS SyncFIFOTM 512 x 36 1,024 x 36 IDT72V3631 IDT72V3641 FEATURES • Storage capacity: IDT72V3631 - 512 x 36 IDT72V3641 - 1,024 x 36 • Supports clock frequencies up to 67 MHz • Fast access times of 10ns • Free-running CLKA and CLKB can be asynchronous or coinci- dent (permits simultaneous reading and writing of data on a single clock edge) • Clocked FIFO buffering data from Port A to Port B • Synchronous read retransmit capability • Mailbox register in each direction • Programmable Al.

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3.3 VOLT CMOS SyncFIFOTM 512 x 36 1,024 x 36 IDT72V3631 IDT72V3641 FEATURES • Storage capacity: IDT72V3631 - 512 x 36 IDT72V3641 - 1,024 x 36 • Supports clock frequencies up to 67 MHz • Fast access times of 10ns • Free-running CLKA and CLKB can be asynchronous or coinci- dent (permits simultaneous reading and writing of data on a single clock edge) • Clocked FIFO buffering data from Port A to Port B • Synchronous read retransmit capability • Mailbox register in each direction • Programmable Almost-Full and Almost-Empty flags • Microprocessor interface control logic • Input Ready (IR) and Almost-Full (AF) flags synchronized by CLKA • Output Ready (OR) and Almost-Empty (AE) flags synchronized by CLKB FUNCTIONAL BLOCK DIAGRAM • Available in space-saving 120-pin thin quad flat package (TQFP) • Pin and functionally compatible versions of the 5V operating IDT723631/723641 • Easily expandable in width and depth • Green parts are available, see ordering information DESCRIPTION The IDT72V3631/72V3641 are pin and functionally compatible versons of the IDT723631/723641, designed to run off a 3.3V supply for exceptionally lowpower consumption. These devices are monolithic high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 10ns. The 512/1,024 x 36 dual-port SRAM FIFO buffers data from port A to Port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO operates in First Word Fall Through mode and has flags to indicate empty and full conditions and conditions and two programmable flags (Almost-Full and Almost-Empty) to indicate when a selected number of words is stored in memory. CLKA CSA W/RA ENA MBA Port-A Control Logic Mail 1 Register RAM ARRAY 512 x 36 1,024 x 36 MBF1 Output Register Input Register RST Reset Logic 36 A0 - A35 IR AF Write Read Pointer Pointer Status Flag Logic Sync Retransmit Logic RTM RFM B0 - B35 OR AE FS0/SD FS1/SE N Flag Offset Registers 10 Mail 2 Register MBF2 IDT and the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 11 © 2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. Port-B Control Logic CLKB CSB W/RB ENB MBB 4658 drw 01 JUNE 2014 DSC-4658/4 IDT72V3631/72V3641 3.3V CMOS SYNCFIFO™ 512 x 36 and 1,024 x 36 COMMERCIAL TEMPERATURE RANGE DESCRIPTION (CONTINUED) Communication between each port may take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices may be used in parallel to create wider data paths. Expansion is also possible in word depth. These devices are a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the LOWto-HIGH transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control. The Input Ready (IR) flag and Almost-Full (AF) flag of the FIFO are two-stage synchronized to CLKA. The Output Ready (OR) flag and Almost-Empty (AE) flag of the FIFO are two-stage synchronized to CLKB. Offset values for the Almost-Full and Almost-Empty flags of the FIFO can be programmed from port A or through a serial input. The IDT72V3631/72V3641 are characterized for operation from 0°C to 70°C. These devices are fabricated using high speed, submicron CMOS technology. PIN CONFIGURATION 91 VCC 92 CLKB 93 ENB 94 W/RB 96 GND 95 CSB 97 MBF1 98 GND 99 MBB 100 NC 101 VCC 102 RFM 103 RTM FS0/SD FS1/SEN 106 GND VCC MBF2 MBA RST VCC AF AE 114 OR ENA W/RA CSA 115 IR 119 CLKA 120 GND 105 104 110 109 108 107 113 112 111 118 117 116 A35 1 A34 2 A33 3 A32 4 VCC 5 A31 6 A30 7 GND 8 A29 9 A28 10 A27 11 A26 12 A25 13 A24 14 A23 15 GND 16 A22 17 VCC 18 A21 19 A20 20 A19 21 A18 22 GND 23 A17 24 A16 25 A15 26 A14 27 A13 28 VCC 29 A12 30 NOTE: 1. NC – No internal connection. GND 31 A11 32 A10 33 A9 34 A8 35 A7 36 A6 37 GND 38 A5 39 A4 40 A3 41 VCC 42 A2 43 A1 44 A0 45 GND 46 B0 47 B1 48 B2 49 B3 50 B4 51 B5 52 GND 53 B6 54 VCC 55 B7 56 B8 57 B9 58 B10 59 B11 60 TQFP (PNG120, order code: PF) TOP VIEW 2 90 B35 89 B34 88 B33 87 B32 86 GND 85 B31 84 B30 83 B29 82 B28 81 B27 80 B26 79 VCC 78 B25 77 B24 76 GND 75 B23 74 B22 73 B21 72 B20 71 B19 70 B18 69 GND 68 B17 67 B16 66 VCC 65 B15 64 B14 63 B13 62 B12 61 GND 4658 drw 03 IDT72V3631/72V3641 3.3V CMOS SYNCFIFO™ 512 x 36 and 1,024 x 36 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION Symbol Name I/O Description A0-A35 Port-A Data I/O 36-bit bidirectional data port for side A. AE Almost-.


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