DatasheetsPDF.com

CD4007C Dataheets PDF



Part Number CD4007C
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description Dual Complementary Pair Plus Inverter
Datasheet CD4007C DatasheetCD4007C Datasheet (PDF)

CD4007C Dual Complementary Pair Plus Inverter October 1987 Revised January 1999 CD4007C Dual Complementary Pair Plus Inverter General Description The CD4007C consists of three complementary pairs of Nand P-channel enhancement mode MOS transistors suitable for series/shunt applications. All inputs are protected from static discharge by diode clamps to VDD and VSS. For proper operation the voltages at all pins must be constrained to be between VSS − 0.3V and VDD + 0.3V at all times. Features s.

  CD4007C   CD4007C



Document
CD4007C Dual Complementary Pair Plus Inverter October 1987 Revised January 1999 CD4007C Dual Complementary Pair Plus Inverter General Description The CD4007C consists of three complementary pairs of Nand P-channel enhancement mode MOS transistors suitable for series/shunt applications. All inputs are protected from static discharge by diode clamps to VDD and VSS. For proper operation the voltages at all pins must be constrained to be between VSS − 0.3V and VDD + 0.3V at all times. Features s Wide supply voltage range: 3.0V to 15V s High noise immunity: 0.45 VCC (typ.) Ordering Code: Order Number Package Number Package Description CD4007CM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow CD4007CN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS–001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC Note: All P-channel substrates are connected to VDD and all N-channel substrates are connected to VSS. Top View © 1999 Fairchild Semiconductor Corporation DS005943.prf www.fairchildsemi.com CD4007C Absolute Maximum Ratings(Note 1) Voltage at Any Pin Operating Temperature Range Storage Temperature Range Power Dissipation (PD) Dual-In-Line Small Outline VSS −0.3V to VDD +0.3V −40°C to +85°C −65°C to +150°C Operating VDD Range Lead Temperature (Soldering, 10 seconds) VSS +3.0V to VSS +15V 260°C 700 mW 500 mW Note 1: This device should not be connected to circuits with the power on because high transient voltages may cause permanent damage. DC Electrical Characteristics Symbol Parameter IL Quiescent Device Current PD Quiescent Device Dissipation Package VOL Output Voltage LOW Level VOH Output Voltage HIGH Level VNL Noise Immunity (All inputs) VNH Noise Immunity (All Inputs) IDN Output Drive Current N-Channel IDP Output Drive Current P-Channel II Input Current Limits Conditions −40°C +25°C +85°C Units Min Typ Max Min Typ Max Min Typ Max VDD = 5.0V VDD = 10V VDD = 5.0V VDD = 10V VDD = 5.0V VDD = 10V VDD = 5.0V VDD = 10V VDD = 5.0V, VO = 3.6V VDD = 10V, VO = 7.2V VDD = 5.0V, VO = 0.95V VDD = 10V, VO = 2.9V VDD = 5.0V, VO = 0.4V, VI = VDD VDD = 10V, VO = 0.5V, VI = VDD VDD = 5.0V, VO = 2.5V, VI = VSS VDD = 10V, VO = 9.5V, VI = VSS 4.95 9.95 3.6 7.1 0.35 1.2 −1.3 −0.65 0.5 0.005 0.05 1.0 0.005 1.0 2.5 0.025 2.5 10 0.05 10 0.05 0 0.01 0.05 0 0.01 4.95 5.0 4.95 9.95 10 9.95 1.5 2.25 1.5 3.0 4.5 3.0 3.5 2.25 3.5 7.0 4.5 7.0 0.3 1.0 0.24 1.0 2.5 0.8 −1.1 −4.0 −0.9 −0.55 −2.5 −0.45 10 15 µA 30 µA 75 µW 300 µW 0.05 V 0.05 V V V 1.4 V 2.9 V V V mA mA mA mA pA AC Electrical Characteristics (Note 2) TA = 25°C and CL = 15 pF and rise and fall times = 20 ns. Typical temperature coefficient for all values of VDD = 0.3%/°C Symbol Parameter Conditions Min Typ Max Units tPLH = tPHL Propagation Delay Time tTLH.


TL074I CD4007C CD4007CM


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)