74ALVC14PW

74ALVC14 Hex inverting Schmitt trigger Rev. 4 — 14 August 2018 Product data sheet 1. General description The 74ALVC14 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74ALVC14 provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. 2. Features and benefits Wide supply voltage range from 1.65 V to 3.6 V 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Unlimited input rise and fall times Latch-up performance exceeds 250 mA Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM EIA/JESD22-A114-B exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V Multiple package options 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description 74ALVC14D -40 °C to +85 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm 74ALVC14PW -40 °C to +85 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm 74ALVC14BQ -40 °C to +85 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm Version SOT108-1 SOT402-1 SOT762-1 Nexperia 4. Functional diagr...