74ALVCH16823DGG

74ALVCH16823 18-bit bus-interface D-type flip-flop with reset and enable; 3-state Rev. 3 — 1 February 2018 Product data sheet 1 General description The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The 74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock (nCP) input, an output-enable (nOE) input, a master reset (nMR) input and a clockenable (nCE) input are provided for each total 9-bit section. With the clock-enable (nCE) input LOW, the D-type flip-flops will store the state of their individual nDn-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH nCP transition. Taking nCE HIGH disables the clock buffer, thus latching the outputs. Taking the master reset (nMR) input LOW causes all the nQn outputs to go LOW independently of the clock. When nOE is LOW, the contents of the flip-flops are available at the outputs. When the nOE is HIGH, the outputs go to the high impedance OFF-state. Operation of the nOE input does not affect the state of flip-flops. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. 2 Features and benefits Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels Current drive ± 24 mA at...