74ALVCH16952DGG

74ALVCH16952 16-bit registered transceiver; 3-state Rev. 3 — 9 January 2018 Product data sheet 1 General description The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Data applied to the inputs is entered and stored on the rising edge of the clock (nCPAB and nCPBA) provided that the clock enable (nCEAB and nCEBA) is LOW. The data is then present at the output buffers, but is only accessible when the output enable input (nOEAB and nOEBA) is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs. 2 Features and benefits CMOS low-power consumption Multibyte flow-through pinout architecture Low inductance, multiple center power and ground pins for minimum noise and ground bounce Direct interface with TTL levels Output drive capability 50 Ω transmission lines at 85 °C Complies with JEDEC standard JESD8-B 3 Ordering information Table 1. Ordering information Type number Package Temperature range 74ALVCH16952DGG -40 °C to +85 °C Name TSSOP56 Description plastic thin shrink small outline package; 56 leads; body width 6.1 mm Version SOT364-1 Nexperia 74ALVCH16952 16-bit registered transceiver; 3-state 4 Functional diagram 1A0 5 1A1 6 1A2 8 1A3 9 1A4 10 1A5 12 1A6 13 1A7 14 52 1B0 51 1B1 49 1B2 48 1B3 47 1B4 45 1B5 44 1B6 43 1B7 2A0 15 2A1 16 2A2 17 2A3 19 2A4 20 2A5...