SN74AHC125D

SN54AHC125, SN74AHC125 SCLS256O – DECEMBER 1995 – REVISED FEBRUARY 2024 SNx4AHC125 Quadruple Bus Buffer Gates With 3-State Outputs 1 Features Operating range of 2V to 5.5V Latch-up performance exceeds 250mA per JESD 17 Four individual output enable pins 2 Applications Flow Meters Programmable Logic Controllers Power Over Ethernet (PoE) Motor Drives and Controls Electronic Point-of-Sale 3 Description The SNx4AHC125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable ( OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output. To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Device Information PART NUMBER PACKAGE(1) BODY SIZE(2) J (CDIP, 14) 8.89mm 8.89mm SN54AHC125 W (CFP, 14) 19.56mm × 6.67mm FK (LCCC, 20) 9.21mm × 5.97mm DB (SSOP, 14) 6.20mm 5.30mm D (SOIC, 14) 8.65mm × 3.91mm NS (SO, 14) 10.30mm × 5.30mm SN74AHC125 DGV (TVSOP, 14) PW (TSSOP, 14) 3.60mm × 4.40mm 5.00mm × 4.40mm N (PDIP, 14) 19.30mm × 6.35mm RGY (VQFN, 14) 3.50mm × 3.50mm BQA (WQFN, 14) 3mm × 2.5mm (1) For more information, see Section 11. (2) The body size (length × width) is a nominal value and does not include pins. Pin numbers shown are for the D, DB, D...