SNJ54HCT139W

SN54HCT139, SN74HCT139 DUAL 2ĆLINE TO 4ĆLINE DECODERS/DEMULTIPLEXERS D Operating Voltage Range of 4.5 V to 5.5 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 10 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max D Inputs Are TTL-Voltage Compatible D Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems D Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception description/ordering information The ’HCT139 devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. SCLS066D − MARCH 1982 − REVISED SEPTEMBER 2003 SN54HCT139 . . . J OR W PACKAGE SN74HCT139 . . . D, DB, N, OR PW PACKAGE (TOP VIEW) 1G 1 1A 2 1B 3 1Y0 4 1Y1 5 1Y2 6 1Y3 7 GND 8 16 VCC 15 2G 14 2A 13 2B 12 2Y0 11 2Y1 10 2Y2 9 2Y3 SN54HCT139 . . . FK PACKAGE (TOP VIEW) 2G VCC NC 1G 1A 1B 3 2 1 20 19 4 18 2A 1Y0 5 17 2B NC 6 16 NC 1Y1 7 15 2Y0 1Y2 8 14 2Y1 9 10 11 12 13 2Y2 2Y3 NC GND 1Y3 NC − No internal connection ORDERING INFORMATION ...