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TLK105L, TLK106L
SLLSEE3D – AUGUST 2013 – REVISED APRIL 2016
TLK10xL Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver
1 Device Overview
1.1 Features
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• Low-Power Consumption: – Single Supply: <205 mW PHY, 275 mW With Center Tap (Typical) – Dual Supplies: <126 mW PHY, 200 mW With Center Tap (Typical)
• Programmable Power Back Off to Reduce PHY Power up to 20% in Systems With Shorter Cables
• IEEE 1588 SFD Indication Enables Time Stamping by a Controller or Processor
• Low Deterministic Latency Supports IEEE1588 Implementation
• Cable Diagnostics • Programmable Fast Link Down Modes, <10 µs
Reaction Time • Variable I/O voltage range: 3.3V, 2.5V, 1.8V • MAC Interface I/O voltage range:
– MII I/O voltage range: 3.3V, 2.5V, 1.8V – RMII I/O voltage range: 3.3V, 2.5V • Fixed TX Clock to XI, With Programmable Phase Shift • Auto-MDIX for 10/100Mbs • Energy Detection Mode • MII and RMII Capabilities • IEEE 802.3u MII
• Error-Free 100Base-T Operation up to 150 Meters Under Typical Conditions
• Error-Free 10Base-T Operation up to 300 Meters Under Typical Conditions
• Serial Management Interface
• IEEE 802.3u Auto-Negotiation and Parallel Detection
• IEEE 802.3u ENDEC, 10Base-T Transceivers and Filters
• IEEE 802.3u PCS, 100Base-TX Transceivers
• Integrated ANSI X3.263 Compliant TP-PMD Physical Sublayer with Adaptive Equalization and Baseline Wander Compensation
• Programmable LED Support Link, Activity
• 10/100Mbs Packet BIST (Built in Self Test)
• HBM ESD Protection on RD± and TD± of 16 kV
• 32-pin VQFN (5 mm) × (5 mm)
1.2 Applications • Industrial Networks and Factory Automation • Motor and Motion Control
• General Embedded Applications
1.3 Description
The TLK10xL is a single-port Ethernet PHY for 10Base-T and 100Base TX signaling, integrating all the physical-layer functions needed to transmit and receive data on standard twisted-pair cables. The device supports the standard Media Independent Interface (MII) and Reduced Media Independent Interface (RMII) for direct connection to a Media Access Controller (MAC).
The device is designed for power-supply flexibility, and can operate with a single 3.3-V power supply or with combinations of 3.3-V and 1.55-V power supplies for reduced power operation.
The TLK10xL uses mixed-signal processing to perform equalization, data recovery, and error correction to achieve robust operation over CAT 5 twisted-pair wiring. The TLK10xL not only meets the requirements of IEEE 802.3, but maintains high margins in terms of cross-talk and alien noise.
The TLK10xL Ethernet PHY has a special Power Back Off mode to conserve power in systems with relatively short cables. This mode provides the flexibility to reduce system power when the system is not required to drive the standard IEEE 802.3 100-m cable length, or the extended 150m, error-free cable reach of the TLK10xL. For more detail, see application note SLLA328.
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLK105L, TLK106L
SLLSEE3D – AUGUST 2013 – REVISED APRIL 2016
TLK10xL
www.ti.com
10BASE-T or
100BASE-TX
Copyright © 2016, Texas Instruments Incorporated
PART NUMBER
Device Information(1)
PACKAGE
TLK10xL
VQFN (32)
(1) For more information, see Section 8, Mechanical Packaging and Orderable Information.
BODY SIZE 5.00 mm × 5.00 mm
2
Device Overview
Copyright © 2013–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK105L TLK106L
www.ti.com
1.4 Functional Block Diagram
MII Option
TLK105L, TLK106L
SLLSEE3D – AUGUST 2013 – REVISED APRIL 2016
RMII Option
MII/RMII Interface
100BASE-T
100BASE-T
Cable Diagnostics
Copyright © 2016, Texas Instruments Incorporated
Figure 1-1. TLK10xL Functional Block Diagram
Copyright © 2013–2016, Texas Instruments Incorporated Submit Documentation Feedback
Product Folder Links: TLK105L TLK106L
Device Overview
3
TLK105L, TLK106L
SLLSEE3D – AUGUST 2013 – REVISED APRIL 2016
www.ti.com
Table of Contents
1 Device Overview ......................................... 1 1.1 Features .............................................. 1 1.2 Applications........................................... 1 1.3 Description............................................ 1 1.4 Functional Block Diagram ............................ 3
2 Revision History ........................................ 4 3 Pin Configuration and Functions..................... 7
3.1 Pin Diagram .......................................... 7 3.2 Serial Management Interface (SMI) .................. 8 3.3 MAC Data Interface .................................. 8 3.4 10Mbs and 100Mbs PMD Interface .................. 9 3.5 Clock Interface .....