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813N252I-09
Datasheet
General Description
The 813N252I-09 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClock™frequency multiplier that provides the low jitter, high frequency Ethernet output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET and Ethernet applications. The VCXO requires the use of an external, inexpensive pullable crystal. The VCXO uses external passive loop filter components which allows configuration of the PLL loop bandwidth and damping characteristics. The device is packaged in a space-saving 32-VFQFN package and supports industrial temperature range.
Features
• Two LVPECL output pairs
Each output supports independent frequency selection at 25MHz, 125MHz, 156.25MHz and 312.5MHz
• Two differential inputs support the following input types: LVPECL,
LVDS, LVHSTL, SSTL, HCSL
• Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz, 125MHz and 155.52MHz
• Attenuates the phase jitter of the input clock by using a low-cost
pullable fundamental mode VCXO crystal
• VCXO PLL bandwidth can be optimized for jitter attenuation and
reference tracking using external loop filter connection
• FemtoClock frequency multiplier provides low jitter, high frequency
output
• Absolute pull range: 50ppm
• FemtoClock VCO frequency: 625MHz
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(12kHz – 20MHz): 0.25ps (typical) and 0.35ps (maximum)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Pin Assignment
VCCX XTAL_IN XTAL_OUT CLK0 nCLK0 VCC CLK1 nCLK1
32 31 30 29 28 27 26 25
LF1 1
24 VEE
LF0 2
23 nQB
ISET 3
22 QB
VEE 4
21 VCCO
CLK_SEL 5
20 nQA
VCC 6
19 QA
RESERVED 7
18 VEE
VEE 8
17 ODASEL_0
9 10 11 12 13 14 15 16
PDSEL_2 PDSEL_1 PDSEL_0
VCC VCCA ODBSEL_1 ODBSEL_0 ODASEL_1
813N252I-09 32 Lead VFQFN 5mm x 5mm x 0.925mm package body 3.15mm x 3.15mm EPad
K Package Top View
©2015 Integrated Device Technology, Inc.
1
Revision C, December 10, 2015
Block Diagram
Loop Filter
813N252I-09 Datasheet
ISET LF0 LF1
XTAL_IN XTAL_OUT
PDSEL_[2:0] Pullup
CLK0 Pulldown nCLK0 PU/PD
CLK1 Pulldown nCLK1 PU/PD CLK_SEL Pulldown
25MHz
VCXO Input
0
Pre-Divider
000 = 1
Phase Detector
001 = 193
VCXO
010 = 256 1 011 = 2430
Charge Pump
100 = 3125 101 = 9720 110 = 15625
VCXO Feedback Divider ÷3125
111 = 19440
(default)
VCXO Jitter Attenuation PLL
FemtoClock PLL 625MHz
Output Divider
00 = 25 (default) 01 = 5 10 = 4 11 = 2
2 Pulldown
QA nQA
ODASEL_[1:0]
Output Divider
00 = 25 (default) 01 = 5 10 = 4 11 = 2
2 Pulldown
QB nQB
ODBSEL_[1:0]
©2015 Integrated Device Technology, Inc.
2
Revision C, December 10, 2015
813N252I-09 Datasheet
Pin Description and Pin Characteristics Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
LF1, LF0
Analog Input/Output
Loop filter connection node pins. LF0 is the output. LF1 is the input.
3
ISET
Analog Input/Output
Charge pump current setting pin.
4, 8, 18, 24 5
VEE CLK_SEL
Power Input
Pulldown
Negative supply pins.
Input clock select. When HIGH selects CLK1, nCLK1. When LOW, selects CLK0, nCLK0. LVCMOS / LVTTL interface levels.
6, 12, 27 7
VCC RESERVED
Power Reserved
Core supply pins. Reserved pin. Do not connect.
9,
PDSEL_2,
10,
PDSEL_1,
Input
11
PDSEL_0
Pullup Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A.
13
VCCA
Power
Analog supply pin.
14, 15
ODBSEL_1, ODBSEL_0
Input
Pulldown
Frequency select pins for Bank B output. See Table 3B. LVCMOS/LVTTL interface levels.
16, 17
ODASEL_1, ODASEL_0
Input
Pulldown
Frequency select pins for Bank A output. See Table 3B. LVCMOS/LVTTL interface levels.
19, 20
QA, nQA
Output
Differential Bank A clock outputs. LVPECL interface levels.
21 22, 23
VCCO QB, nQB
Power Output
Output supply pin. Differential Bank B clock outputs. LVPECL interface levels.
25
nCLK1
Input
Pullup/ Pulldown
Inverting differential clock input. VCC/2 bias voltage when left floating.
26
CLK1
Input
Pulldown Non-inverting differential clock input.
28
nCLK0
Input
Pullup/ Pulldown
Inverting differential clock input. VCC/2 bias voltage when left floating.
29
CLK0
Input
Pulldown Non-inverting differential clock input.
30, 31
XTAL_OUT, XTAL_IN
Input
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
32
VCCX
Power
P.