SNJ54HC377J

D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 12 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max D Eight Flip-Flops With Single-Rail Outputs D Clock Enable Latched to Avoid False Clocking D Applications Include: – Buffer/Storage Registers – Shift Registers – Pattern Generators description/ordering information These devices are positive-edge-triggered octal D-type flip-flops with an enable input. The ’HC377 devices are similar to the ’HC273 devices, but feature a latched clock-enable (CLKEN) input instead of a common clear. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse, if CLKEN is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN. 4Q GND CLK 5Q 5D SN54HC377, SN74HC377 OCTAL DĆTYPE FLIPĆFLOPS WITH CLOCK ENABLE SCLS307B– JANUARY 1996 – REVISED JANUARY 2003 SN54HC377 . . . J OR W PACKAGE SN74HC377 . . . DW, N, OR NS PACKAGE (TOP VIEW) CLKEN 1 1Q 2 1D 3 2D 4 2Q 5 3Q 6 3D 7 4D 8 4Q 9 GND 10 20 VCC 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 CLK SN54HC377 . . . FK PACKAGE (TOP VIEW) 1D 1Q CLKEN VCC 8Q 2D ...