configurable gate. 74AUP1T97GX Datasheet

74AUP1T97GX gate. Datasheet pdf. Equivalent


nexperia 74AUP1T97GX
74AUP1T97
Low-power configurable gate with voltage-level translator
Rev. 6 — 28 March 2017
Product data sheet
1 General description
The 74AUP1T97 provides low-power, low-voltage configurable logic gate functions. The
output state is determined by eight patterns of 3-bit input. The user can choose the logic
functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected
to VCC or GND.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 2.3 V to 3.6 V.
The 74AUP1T97 is designed for logic-level translation applications with input switching
levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single
2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from
3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the
device when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across
the entire VCC range.
2 Features and benefits
Wide supply voltage range from 2.3 V to 3.6 V
High noise immunity
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5 000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1 000 V
Low static power consumption; ICC = 1.5 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C


74AUP1T97GX Datasheet
Recommendation 74AUP1T97GX Datasheet
Part 74AUP1T97GX
Description Low-power configurable gate
Feature 74AUP1T97GX; 74AUP1T97 Low-power configurable gate with voltage-level translator Rev. 6 — 28 March 2017 Produc.
Manufacture nexperia
Datasheet
Download 74AUP1T97GX Datasheet




nexperia 74AUP1T97GX
Nexperia
74AUP1T97
Low-power configurable gate with voltage-level translator
3 Ordering information
Table 1. Ordering information
Type number Package
Temperature
range
74AUP1T97GW -40 °C to +125 °C
74AUP1T97GM -40 °C to +125 °C
74AUP1T97GF -40 °C to +125 °C
74AUP1T97GN -40 °C to +125 °C
74AUP1T97GS -40 °C to +125 °C
74AUP1T97GX -40 °C to +125 °C
74AUP1T97UK -40 °C to +125 °C
Name Description
SC-88 plastic surface-mounted package; 6 leads
XSON6 plastic extremely thin small outline package;
no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
XSON6 plastic extremely thin small outline package;
no leads; 6 terminals; body 1 x 1 x 0.5 mm
XSON6 extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm
XSON6 extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm
X2SON6 plastic thermal extremely thin small
outline package; no leads; 6 terminals;
body 1 x 0.8 x 0.35 mm
WLCSP6 wafer level chip-scale package; 6 bumps;
0.65 x 0.44 x 0.27 mm
4 Marking
Table 2. Marking
Type number
74AUP1T97GW
74AUP1T97GM
74AUP1T97GF
74AUP1T97GN
74AUP1T97GS
74AUP1T97GX
74AUP1T97UK
Marking code[1]
59
59
59
59
59
59
9
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
Version
SOT363
SOT886
SOT891
SOT1115
SOT1202
SOT1255
SOT1454-1
74AUP1T97
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 28 March 2017
© Nexperia B.V. 2017. All rights reserved.
2 / 23



nexperia 74AUP1T97GX
Nexperia
5 Pinning information
74AUP1T97
Low-power configurable gate with voltage-level translator
5.1 Pinning
Table 3. Pinning
74AUP1T97
B1
6C
GND 2
5 VCC
A3
4Y
001aag500
Figure 1. Pin configuration SOT363 (SC-88)
74AUP1T97
B1
6C
GND 2
5 VCC
A3
4Y
001aag502
Transparent top view
Figure 3. Pin configuration SOT891, SOT1115 and
SOT1202 (XSON6)
74AUP1T97UK
ball A1
index area
1
2
A
B
C
aaa-018292
Transparent top view
Figure 5. Pin configuration SOT1454-1 (WLCSP6)
74AUP1T97
B1
6C
GND 2
5 VCC
A3
4Y
001aag501
Transparent top view
Figure 2. Pin configuration SOT886 (XSON6)
74AUP1T97
B
C
1
6
GND
2
5
VCC
3
4
A
Y
aaa-019832
Transparent top view
Figure 4. Pin configuration SOT1255 (X2SON6)
74AUP1T97UK
1
2
AB
C
B GND VCC
CA
Y
aaa-018293
Transparent top view
Figure 6. Ball mapping for SOT1454-1 (WLCSP6)
74AUP1T97
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 28 March 2017
© Nexperia B.V. 2017. All rights reserved.
3 / 23







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