Document
DATASHEET
82C52
CMOS Serial Controller Interface
FN2950 Rev 4.00 November 25, 2015
The Intersil 82C52 is a high performance programmable Universal Asynchronous Receiver/Transmitter (UART) and Baud Rate Generator (BRG) on a single chip. Utilizing the Intersil advanced Scaled SAJI IV CMOS process, the 82C52 will support data rates up to 1M baud asynchronously with a 16X clock (16MHz clock frequency).
The on-chip Baud Rate Generator can be programmed for any one of 72 different baud rates using a single industry standard crystal or external frequency source. A unique pre-scale divide circuit has been designed to provide standard RS-232-C baud rates when using any one of three industry standard crystals (1.8432MHz, 2.4576MHz, or 3.072MHz).
Features
• Single Chip UART/BRG • DC to 16MHz (1M Baud) Operation • Crystal or External Clock Input • On-Chip Baud Rate Generator - 72 Selectable Baud Rates • Interrupt Mode with Mask Capability • Microprocessor Bus Oriented Interface • 80C86 Compatible • Single +5V Power Supply
A programmable buffered clock output (CO) is available and can be programmed to provide either a buffered oscillator or 16X baud rate clock for general purpose system usage.
• Low Power Operation . . . . . . . . . . . . . . . . . . . . 1mA/MHz Typ • Modem Interface • Line Break Generation and Detection
• Operating Temperature Range: - C82C52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0°C to +70°C - I82C52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C - M82C52. . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
• Pb-Free Plus Anneal Available (RoHS Compliant)
•
Ordering Information
1M BAUD
PART MARKING
TEMP RANGE (°C)
PACKAGE
PKG. DWG. #
CP82C52 (No longer available or supported Recommended Replacement: CP82C52Z)
CP82C52
0 to +70
PDIP
E28.6
CP82C52Z (Note)
CP82C52Z
0 to +70
PDIP (Pb-Free)**
E28.6
IP82C52
IP82C52
-40 to +85
PDIP
E28.6
CS82C5296
CS82C52
0 to +70
PLCC (Tape & Reel)
N28.45
CS82C52Z* (Note)
CS82C52Z
0to +70
PLCC (Pb-Free)
N28.45
IS82C52
IS82C52
-40 to +85
PLCC
N28.45
IS82C52Z* (Note)
IS82C52Z
-40 to +85
PLCC (Pb-Free)
N28.45
ID82C52
ID82C52
-40 to +85
CERDIP
F28.6
MD82C52/B
MD82C52/B
-55 to +125
F28.6
8501501XA
8501501XA
SMD#
F28.6
MR82C52/B
-55 to +125
CLCC
J28.A
85015013A
85015013A
SMD#
J28.A
*Add "96" suffix for tape and reel.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN2950 Rev 4.00 November 25, 2015
Page 1 of 21
82C52
Pinouts
82C52 (PDIP, CERDIP) TOP VIEW
RD 1 WR 2 D0 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 10 A0 11 A1 12
IX 13 OX 14
28 CSO 27 VCC 26 DR 25 SDI 24 INTR 23 RST 22 TBRE 21 CO 20 RTS 19 DTR 18 DSR 17 CTS 16 GND 15 SDO
Block Diagram
D0-D7
3 - 10
RD
1
WR
2
A0
11
A1
12
CSO
28
IX
13
OX
14
CO
21
RST
23
INTR
24
DATA BUS BUFFER READ/WRITE CONTROL LOGIC PROGRAMMABLE BOUD RATE GENERATOR CONTROL LOGIC
INTERNAL DATA BUS A1 IX OX
SDO GND CTS DSR
82C52 (PLCC, CLCC) TOP VIEW
D1 D0 WR RD CSO VCC DR
4 3 2 1 28 27 26
D2 5
25 SDI
D3 6
24 INTR
D4 7
23 RST
D5 8 D6 9
22 TBRE 21 CO
D7 10
20 RTS
A0 11
19 DTR
12 13 14 15 16 17 18
UART CONTROL AND
STATUS REGISTERS TRANSMITTER
BUFFER REGISTER RECEIVER
BUFFER REGISTER
MODEM CONTROL AND
STATUS REGISTERS
22
TBRE
26
DR
TRANSMITTER
REGISTER
P
S
15
SDO
RECEIVER
REGISTER
P
S
25
SDI
18
DSR
17
CTS
19
DTR
20
RTS
FN2950 Rev 4.00 November 25, 2015
Page 2 of 21
82C52
Pin Description
PIN SYMBOL NO. TYPE
RD
1
I
WR
2
I
D0-D7
3-10
I/O
A0, A1 11, 12
I
IX, OX 13, 14 I/O
SDO
15
O
GND
16
CTS
17
I
DSR
18
I
DTR
19
O
RTS
20
O
CO
21
O
TBRE
22
O
RST
23
I
INTR
24
O
ACTIVE LEVEL
DESCRIPTION
Low READ: The RD input causes the 82C52 to output data to the data bus (D0-D7). The data output depends upon the state of the address inputs (A0-A1). CS0 enables the RD input.
Low WRITE: The WR input causes data from the data bus (D0-D7) to be input to the 82C52. Addressing and chip select action is the same as for read operations.
High
DATA BITS 0-7: The Data Bus provides eight, three-state input/output lines for the transfer of data, control and status information between the 82C52 and the CPU. For character formats of less than 8 bits, the corresponding D7, D6 and D5 are considered “don't cares” for data WRITE operations and are 0 for data READ operations. These lines are normally in a high impedance stat.