Document
PCA9665; PCA9665A
Fm+ parallel bus to I2C-bus controller
Rev. 4 — 29 September 2011
Product data sheet
1. General description
The PCA9665/PCA9665A serves as an interface between most standard parallel-bus microcontrollers/microprocessors and the serial I2C-bus and allows the parallel bus system to communicate bidirectionally with the I2C-bus. The PCA9665/PCA9665A can operate as a master or a slave and can be a transmitter or receiver. Communication with the I2C-bus is carried out on a Byte or Buffered mode using interrupt or polled handshake. The PCA9665/PCA9665A controls all the I2C-bus specific sequences, protocol, arbitration and timing with no external timing element required.
The PCA9665 and PCA9665A have the same footprint as the PCA9564 with additional features:
• 1 MHz transmission speeds • Up to 25 mA drive capability on SCL/SDA • 68-byte buffer • I2C-bus General Call • Software reset on the parallel bus
2. Features and benefits
Parallel-bus to I2C-bus protocol converter and interface Both master and slave functions Multi-master capability Internal oscillator trimmed to 15 % accuracy reduces external components 1 Mbit/s and up to 25 mA SCL/SDA IOL (Fast-mode Plus (Fm+)) capability I2C-bus General Call capability Software reset on parallel bus 68-byte data buffer Operating supply voltage: 2.3 V to 3.6 V 5 V tolerant I/Os Standard-mode and Fast-mode I2C-bus capable and compatible with SMBus PCA9665A ‘glitch-free’ restart is suitable for use with buffer drivers ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered:
PCA9665: SO20, TSSOP20, HVQFN20 PCA9665A: TSSOP20
NXP Semiconductors
PCA9665; PCA9665A
Fm+ parallel bus to I2C-bus controller
3. Applications
Add I2C-bus port to controllers/processors that do not have one Add additional I2C-bus ports to controllers/processors that need multiple I2C-bus ports Converts 8 bits of parallel data to serial data stream to prevent having to run a large
number of traces across the entire printed-circuit board
4. Ordering information
Table 1. Ordering information Tamb = 40 C to +85 C.
Type number Topside mark
Package Name
PCA9665BS 9665
HVQFN20
PCA9665D PCA9665PW
PCA9665D SO20 PCA9665 TSSOP20
PCA9665APW CA9665A TSSOP20
Description
Version
plastic thermal enhanced very thin quad flat package; no leads; SOT662-1 20 terminals; body 5 5 0.85 mm
plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
PCA9665_PCA9665A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2011
© NXP B.V. 2011. All rights reserved.
2 of 92
NXP Semiconductors
5. Block diagram
PCA9665; PCA9665A
Fm+ parallel bus to I2C-bus controller
PCA9665/PCA9665A
SDA
FILTER
data D7 D6 D5 D4 D3 D2 D1 D0
BUS BUFFER
SDA CONTROL
68-BYTE BUFFER
SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 I2CDAT – data register – read/write
AA ENSIO STA STO SI
SCL
FILTER
–
–
–
–
– IP2 IP1 IP0
INDPTR – indirect address pointer – write only
ST5 ST4 ST3 ST2 ST1 ST0 0
0
I2CSTA – status register – read only
SCL CONTROL
AA ENSIO STA STO SI
–
– MODE
I2CCON – control register – read/write
ENSIO STA STO SI
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 INDIRECT – indirect register access – read/write
LB BC6 BC5 BC4 BC3 BC2 BC1 BC0 I2CCOUNT – byte count – read/write
direct registers A1 A0
0
1
0
0
0
0
1
1
1
0
indirect registers INDPTR 00h
AD7 AD6 AD5 AD4 AD3 AD2 AD1 GC
I2CADR – own address – read/write
01h
L7 L6 L5 L4 L3 L2 L1 L0
I2CSCLL – SCL LOW period – read/write
02h
H7 H6 H5 H4 H3 H2 H1 H0
I2CSCLH – SCL HIGH period – read/write
03h
CLOCK SELECTOR OSCILLATOR
TE BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 I2CTO – TIMEOUT register – read/write
IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0 I2CPRESET – software reset register – write only
–
–
–
–
–
– AC1 AC0
I2CMODE – I2C-bus mode register – read/write
INTERRUPT CONTROL
CONTROL BLOCK
04h
05h
06h POWER-ON
RESET
CE
WR
Fig 1. Block diagram of PCA9665/PCA9665A
RD
INT
control signals
RESET A1 A0
002aab023
VDD
PCA9665_PCA9665A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2011
© NXP B.V. 2011. All rights reserved.
3 of 92
NXP Semiconductors
6. Pinning information
6.1 Pinning
PCA9665; PCA9665A
Fm+ parallel bus to I2C-bus controller
D0 1 D1 2 D2 3 D3 4 D4 5 D5 6 D6 7 D7 8 i.c. 9 VSS 10
PCA9665D
20 VDD 19 SDA 18 SCL 17 RESET 16 INT 15 A1 14 A0 13 CE 12 RD 11 WR
002aab020
Fig 2. Pin configuration for SO20
D0 1 D1 2 D2 3 D3 4 D4 5 D5 6 D.