I/O port. PCA9698DGG Datasheet

PCA9698DGG port. Datasheet pdf. Equivalent


NXP PCA9698DGG
PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
Rev. 3 — 3 August 2010
Product data sheet
1. General description
The PCA9698 provides 40-bit parallel input/output (I/O) port expansion for I2C-bus
applications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are capable
of sourcing 10 mA and sinking 25 mA with a total package load of 1 A to allow direct
driving of 40 LEDs. Any of the 40 I/O ports can be configured as an input or output.
The PCA9698 is the first GPIO device in a new Fast-mode Plus (Fm+) family. Fm+
devices offer higher frequency (up to 1 MHz) and longer, more densely populated bus
operation (up to 4000 pF).
The device is fully configurable: output ports can be programmed to be totem-pole or
open-drain and logic states can change at either the Acknowledge (bank change) or the
Stop Command (global change), each input port can be masked to prevent it from
generating interrupts when its state changes, I/O data logic state can be inverted when
read by the system master.
An open-drain interrupt output pin (INT) allows monitoring of the input pins and is asserted
each time a change occurs in one or several input ports (unless masked).
The Output Enable pin (OE) 3-states any I/O selected as output and can be used as an
input signal to blink or dim LEDs (PWM with frequency > 80 Hz and change duty cycle).
A ‘GPIO All Call’ command allows to program multiple Advanced GPIOs at the same time
even if they have different I2C-bus addresses. This allows optimal code programming
when more than one device needs to be programmed with the same instruction or if all
outputs need to be turned on or off at the same time (for example, LED test).
The Device ID, hard coded in the PCA9698, allows the system master to read
manufacturer, part type and revision information.
The SMBus Alert feature allows the SMBALERT pins of multiple devices with this feature
to be connected together to form a wired-AND signal and to be used in conjunction with
the SMBus Alert Response Address.
The internal Power-On Reset (POR) or hardware reset pin (RESET) initializes the 40 I/Os
as inputs. Three address select pins configure one of 64 slave addresses.
The PCA9698 is available in 56-pin TSSOP and HVQFN packages and is specified over
the 40 °C to +85 °C industrial temperature range.
2. Features and benefits
„ 1 MHz Fast-mode Plus I2C-bus serial interface
„ Compliant with I2C-bus Fast-mode (400 kHz) and Standard-mode (100 kHz)


PCA9698DGG Datasheet
Recommendation PCA9698DGG Datasheet
Part PCA9698DGG
Description 40-bit Fm+ I2C-bus advanced I/O port
Feature PCA9698DGG; PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT Rev. 3 — 3 August 2010 Produc.
Manufacture NXP
Datasheet
Download PCA9698DGG Datasheet




NXP PCA9698DGG
NXP Semiconductors
PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
„ 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
„ 40 configurable I/O pins that default to inputs at power-up
„ Outputs:
‹ Programmable totem-pole (10 mA source, 25 mA sink) or open-drain (25 mA sink)
with controlled edge rate output structure. Default to totem-pole on power-up.
‹ Active LOW Output Enable (OE) input pin 3-states all outputs. Polarity can be
programmed to active HIGH through the I2C-bus. Defaults to OE on power-up.
‹ Output state change programmable on the Acknowledge or the STOP Command to
update outputs byte-by-byte or all at the same time respectively. Defaults to
Acknowledge on power-up.
„ Inputs:
‹ Open-drain active LOW Interrupt (INT) output pin allows monitoring of logic level
change of pins programmed as inputs
‹ Programmable Interrupt Mask Control for input pins that do not require an interrupt
when their states change
‹ Polarity Inverter register allows inversion of the polarity of the I/O pins when read
„ Active LOW SMBus Alert (SMBALERT) output pin allows to initiate SMBus ‘Alert
Response Address’ sequence. Own slave address sent when sequence initiated.
„ Active LOW Reset (RESET) input pin resets device to power-up default state
„ GPIO All Call address allows programming of more than one device at the same time
with the same parameters
„ 64 programmable slave addresses using 3 address pins
„ Readable Device ID (manufacturer, device type and revision)
„ Designed for live insertion in PICMG applications
‹ Minimize line disturbance (IOFF and power-up 3-state)
‹ Signal transient rejection (50 ns noise filter and robust I2C-bus state machine)
„ Low standby current
„ 40 °C to +85 °C operation
„ ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
„ Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
„ Packages offered: TSSOP56, and HVQFN56
3. Applications
„ Servers
„ RAID systems
„ Industrial control
„ Medical equipment
„ PLCs
„ Cell phones
„ Gaming machines
„ Instrumentation and test measurement
PCA9698
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 3 August 2010
© NXP B.V. 2010. All rights reserved.
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NXP PCA9698DGG
NXP Semiconductors
PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
4. Ordering information
Table 1. Ordering information
Tamb = 40 °C to +85 °C
Type number Topside mark
PCA9698DGG PCA9698DGG
PCA9698BS
PCA9698BS
Package
Name
TSSOP56
HVQFN56
Description
plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
plastic thermal enhanced very thin quad flat package;
no leads; 56 terminals; body 8 × 8 × 0.85 mm
5. Block diagram
Version
SOT364-1
SOT684-1
OE
PCA9698
AD0
AD1
AD2
SCL
SDA
VDD
VSS
RESET
LOW PASS
INPUT
FILTERS
ADDRESS
DECODER
8-bit
read pulse 0
write pulse 0
INPUT/
OUTPUT
PORTS
BANK 0
I2C-BUS/SMBUS
CONTROL
BANK 1
BANK 2
BANK 3
POWER-ON
RESET
8-bit
read pulse 4
write pulse 4
INPUT/
OUTPUT
PORTS
BANK 4
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
IO4_0
IO4_1
IO4_2
IO4_3
IO4_4
IO4_5
IO4_6
IO4_7
INTERRUPT
MANAGEMENT
LP FILTER
Remark: All I/Os are set to inputs at power-up and RESET.
Fig 1. Block diagram of PCA9698
INT/SMBALERT
002aab935
PCA9698
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 3 August 2010
© NXP B.V. 2010. All rights reserved.
3 of 48







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