Stereo ADC. TLV320ADC3101 Datasheet

TLV320ADC3101 ADC. Datasheet pdf. Equivalent


etcTI TLV320ADC3101
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
Reference
Design
TLV320ADC3101
SLAS553B – NOVEMBER 2008 – REVISED AUGUST 2015
TLV320ADC3101 Low-Power Stereo ADC With Embedded miniDSP
for Wireless Handsets and Portable Audio
1 Features
1 Stereo Audio ADC
– 92-dBA Signal-to-Noise Ratio
– Supports ADC Sample Rates From 8 kHz to
96 kHz
• Instruction-Programmable Embedded miniDSP
• Flexible Digital Filtering With RAM Programmable
Coefficient, Instructions, and Built-In Processing
Blocks
– Low-Latency IIR Filters for Voice
– Linear Phase FIR Filters for Audio
– Additional Programmable IIR Filters for EQ,
Noise Cancellation or Reduction
– Up to 128 Programmable ADC Digital Filter
Coefficients
• Six Audio Inputs With Configurable Automatic
Gain Control (AGC)
– Programmable in Single-Ended or Fully
Differential Configurations
– Can Be 3-Stated for Easy Interoperability With
Other Audio ICs
• Low Power Consumption and Extensive Modular
Power Control:
– 6-mW Mono Record, 8-kHz
– 11-mW Stereo Record, 8-kHz
– 10-mW Mono Record, 48-kHz
– 17-mW Stereo Record, 48-kHz
• Dual Programmable Microphone Bias
• Programmable PLL for Clock Generation
• I2C Control Bus
• Audio Serial Data Bus Supports I2S, Left/Right-
Justified, DSP, PCM, and TDM Modes
• Digital Microphone Input Support
• Two GPIOs
• Power Supplies:
– Analog: 2.6 V to 3.6 V
– Digital: Core: 1.65 V to 1.95 V,
I/O: 1.1 V–3.6 V
• 4-mm × 4-mm 24-Pin RGE (VQFN)
2 Applications
• Wireless Handsets
• Portable Low-Power Audio Systems
• Noise-Cancellation Systems
• Front-End Voice or Audio Processor for Digital
Audio
3 Description
The TLV320ADC3101 device is a low-power, stereo
audio analog-to-digital converter (ADC) supporting
sampling rates from 8 kHz to 96 kHz with an
integrated programmable-gain amplifier providing up
to 40-dB analog gain or AGC. A programmable
miniDSP is provided for custom audio processing.
Front-end input coarse attenuation of 0 dB, –6 dB, or
off, is also provided. The inputs are programmable in
a combination of single-ended or fully differential
configurations. Extensive register-based power
control is available via an I2C interface, enabling
mono or stereo recording. Low power consumption
makes the TLV320ADC3101 ideal for battery-
powered portable equipment.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TLV320ADC3101 VQFN (24)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
Processor
I2C
ADC
ADC
I2S, LJ, RJ, DSP, TDM
miniDSP
Digital Mic
TLV320ADC3101
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.


TLV320ADC3101 Datasheet
Recommendation TLV320ADC3101 Datasheet
Part TLV320ADC3101
Description Low-Power Stereo ADC
Feature TLV320ADC3101; Product Folder Sample & Buy Technical Documents Tools & Software Support & Community Reference .
Manufacture etcTI
Datasheet
Download TLV320ADC3101 Datasheet




etcTI TLV320ADC3101
TLV320ADC3101
SLAS553B – NOVEMBER 2008 – REVISED AUGUST 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Description (continued)......................................... 3
6 Device Comparison Table..................................... 3
7 Pin Configuration and Functions ......................... 4
8 Specifications......................................................... 5
8.1 Absolute Maximum Ratings ...................................... 5
8.2 ESD Ratings.............................................................. 5
8.3 Recommended Operating Conditions....................... 5
8.4 Thermal Information .................................................. 6
8.5 Electrical Characteristics........................................... 6
8.6 Dissipation Ratings .................................................. 7
8.7 I2S/LJF/RJF Timing in Master Mode......................... 8
8.8 DSP Timing in Master Mode ..................................... 8
8.9 I2S/LJF/RJF Timing in Slave Mode........................... 8
8.10 DSP Timing in Slave Mode ..................................... 8
8.11 Typical Characteristics .......................................... 11
9 Parameter Measurement Information ................ 11
10 Detailed Description ........................................... 12
10.1 Overview ............................................................... 12
10.2 Functional Block Diagram ..................................... 13
10.3 Feature Description............................................... 13
10.4 Device Functional Modes...................................... 41
10.5 Programming......................................................... 42
10.6 Register Maps ....................................................... 43
11 Application and Implementation........................ 78
11.1 Application Information.......................................... 78
11.2 Typical Application ............................................... 78
12 Power Supply Recommendations ..................... 82
13 Layout................................................................... 83
13.1 Layout Guidelines ................................................. 83
13.2 Layout Example .................................................... 83
14 Device and Documentation Support ................. 84
14.1 Community Resources.......................................... 84
14.2 Trademarks ........................................................... 84
14.3 Electrostatic Discharge Caution ............................ 84
14.4 Glossary ................................................................ 84
15 Mechanical, Packaging, and Orderable
Information ........................................................... 84
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2009) to Revision B
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Original (November 2008) to Revision A
Page
• Revised column heading for Pin Functions table ................................................................................................................... 4
• Added voltage value for AVDD in Electrical Characteristics condition statement .................................................................. 6
• Added "Input common-mode voltage" to ADC Electrical Characteristics Table..................................................................... 6
• Added voltage value for AVDD in Electrical Characteristics condition statement .................................................................. 7
• Added a row to the Microphone Bias section of the Electrical Characteristics table ............................................................. 7
• Changed Figure 4 - DSP Timing in Slave Mode. Added the WCLK text note. .................................................................... 10
• Changed Figure 9 - Single-Ended Dynamic Range Plot to Input-Referred Noise vs PGA Gain ......................................... 11
• Changed Revised block diagram.......................................................................................................................................... 13
• Added miniDSP Section and miniDSP Information Throughout Datasheet ......................................................................... 14
• Added Figure 40 - 2s Complement Coefficient Format ........................................................................................................ 35
• Changed Data Format for All Control Register Definitions From Decimal To Hex (Binary) ................................................ 43
• Removed note following the page 0 / register 94 description table ..................................................................................... 62
• Changed bit values from 1 and 2 to 0 and 1, respectively. .................................................................................................. 62
• Listed values 81 through 127 as reserved ........................................................................................................................... 62
• Replaced the listing of page 4 registers ............................................................................................................................... 69
• Added a listing for page 5 registers...................................................................................................................................... 73
2
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: TLV320ADC3101



etcTI TLV320ADC3101
www.ti.com
TLV320ADC3101
SLAS553B – NOVEMBER 2008 – REVISED AUGUST 2015
5 Description (continued)
The AGC programs to a wide range of attack (7 ms to 1.4 s) and decay (50 ms to 22.4 s) times. A programmable
noise-gate function is included to avoid noise pumping. Low-latency IIR filters optimized for voice and telephony
are available, as well as linear-phase FIR filters optimized for audio. Programmable IIR filters are also available
and may be used for sound equalization, or to remove noise components. The audio serial bus can be
programmed to support I2S, left-justified, right-justified, DSP, PCM, and TDM modes. The audio bus may be
operated in either master or slave mode.
A programmable integrated PLL is included for flexible clock generation and provides support for all standard
audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz, including the most popular
cases of 12-MHz, 13-MHz, 16-MHz, 19.2-MHz, and 19.68-MHz system clocks.
6 Device Comparison Table
Number of ADCs
Number of Inputs / Outputs
Resolution (Bits)
Control Interface
Digital Audio Interface
Digital Microphone Support
FEATURES
TLV320ADC3101
2
6 / Digital I/F
24
I2C
LJ, RJ, I2S, DSP, TDM
Yes
TLV320ADC3001
2
3 / Digital I/F
24
I2C
LJ, RJ, I2S, DSP, TDM
No
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: TLV320ADC3101
Submit Documentation Feedback
3







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)